Abstract: Methods and apparatus for Enhanced Static IR Drop Analysis are provided. Enhanced Static IR Drop Analysis can be used to determine a quality and robustness of a power distribution network in a circuit. In examples, Enhanced Static IR Drop Analysis includes recording time points at which global current demand profile peaks, sampling instantaneous current from individual tile-based current demand profiles at each time point, and running Static IR Analysis for the tiles at the time points to determine tile current use by the tiles during the time points. Enhanced Static IR Drop Analysis can be used for quick assessment of peak current distribution and determining how the peak current distribution stresses the power distribution network. Enhanced Static IR Drop Analysis is useful during earlier stages of circuit design, when quickly producing circuit performance data is imperative and conventional techniques require significant resources.

Abstract: Specific logic gates for Q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.

Abstract: Specific logic gates for q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.

Abstract: An integrated circuit, or combination of integrated circuits, has a primary interconnect, a redundant interconnect, and circuitry connecting the primary and redundant interconnects allowing selection of the redundant interconnect to bypass the primary interconnect.

Abstract: An integrated circuit configured for at-speed testing is described. The integrated circuit includes a first die. The first die includes a transition launch point. The integrated circuit also includes a second die. The second die includes a first observe point. The integrated circuit further includes a first through silicon via. The first through silicon via couples the first die to the second die.

Abstract: Specific logic gates for q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.

Abstract: An integrated circuit, or combination of integrated circuits, has a primary interconnect, a redundant interconnect, and circuitry connecting the primary and redundant interconnects allowing selection of the redundant interconnect to bypass the primary interconnect.

Abstract: A Built-In Self-Test (BIST) circuit is employed to automatically test integrated analog to digital converters (ADC). Proposed technique applies delta-sigma (&Dgr;&Sgr;) modulator concept to ADC testing and results in a fully automated accurate test procedure suitable for differential non-linearity (DNL) and integral non-linearity (INL) testing. Additional analog circuitry does not have a significant effect on the test accuracy and the test resolution is determined by the sampling frequency of the delta-sigma modulator.

Abstract: n identical integrated circuit blocks are simultaneously tested for defects. Each block contains m scan chains. The ith scan chains in each block are identical (i=1, 2, . . . , m). During an ith clock cycle, an ith test vector is simultaneously applied to each block's ith scan chain. The resultant n output signals are compared. If all n outputs are equal the ith scan chain is designated defect-free for all n blocks; otherwise, the ith scan chain is designated defective for one or more blocks. After sequentially repeating the test vector application, output comparison and designation process for i=1, 2, . . . , m the n blocks are designated defect-free if all m scan chains have been designated defect-free for all n blocks; otherwise, if one or more scan chains have been designated defective for one or more blocks, the n blocks are designated defective.

Abstract: A method and associated circuitry test propagation delay through a path in digital circuits and integrated circuits. The method first sensitizes the target path in the circuit. Then depending on the path a feedback is established between the output and the input of the path to construct an inverting loop. If the path is inverting, the feedback will be noninverting and if the path is noninverting, the feedback will be inverting. The inverting loop or ring carries oscillation signals. In one implementation, the feedback element is connected using a multiplexer coupled to the circuit under test. As the oscillation frequency is determined by the propagation delay through the path, it can be used to measure the path propagation delay. Any kind of faults that can stop the oscillations, such as stuck at faults in the loop, can be detected by observing the oscillation frequency.

Abstract: The oscillation-based test method and device is applied to at least partially analog circuits. The at least partially analog circuit is first divided into building blocks each having a given structure. Each building block is then inserted into an oscillator circuit to produce an output signal having an oscillation frequency related to the structure of the building block under test. The oscillation frequency is then measured and a fault in the building block under test is detected when the measured oscillation frequency deviates from a given, nominal frequency. Experiments have demonstrated that the frequency deviation enables the detection of catastrophic and/or parametric faults, and ensures a high fault coverage. In this new time-domain test method, a single output frequency is evaluated for each building block whereby the test duration is very short. These characteristics make the test strategy very attractive for wafer-probe testing as well as final production testing.