Patents by Inventor Karim Djafarian
Karim Djafarian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8463865Abstract: A digital system is provided that includes a number of hardware accelerators. Each hardware accelerator is paired with a synchronization module that is configured to determine when a scheduled task can be started. Each synchronization module includes a network interface configured to send and receive messages to and from other synchronization modules and a configuration interface configured to receive task information from a host processor. Each synchronization module also includes a task scheduler configured to select a task in response to a received message and a task processor interface configured to initiate the selected task on a hardware accelerator coupled to the synchronization module.Type: GrantFiled: April 21, 2010Date of Patent: June 11, 2013Assignee: Texas Instruments IncorporatedInventors: Franck Seigneret, Claude Marescot, Seyed Karim Djafarian Tehrani, Maija Kuusela, Alain Bruno Chateau
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Publication number: 20110225256Abstract: A digital system is provided that includes a number of hardware accelerators. Each hardware accelerator is paired with a synchronization module that is configured to determine when a scheduled task can be started. Each synchronization module includes a network interface configured to send and receive messages to and from other synchronization modules and a configuration interface configured to receive task information from a host processor. Each synchronization module also includes a task scheduler configured to select a task in response to a received message and a task processor interface configured to initiate the selected task on a hardware accelerator coupled to the synchronization module.Type: ApplicationFiled: April 21, 2010Publication date: September 15, 2011Inventors: Franck Seigneret, Claude Marescot, Seyed Karim Djafarian Tehrani, Maija Kuusela, Alain Bruno Chateau
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Patent number: 6742110Abstract: A processing engine 10 for executing instructions in parallel comprises an instruction buffer 600 for holding at least two instructions, with the first instruction 602 in a first position and the second instruction 604 in a second position. A first decoder 612 provides decoding of the first instruction and generates first control signals. The first control signals include first resource control signals, first address generation control signals, and a first validity signal indicative of the validity of the first instruction in the first position. A second decoder 614 provides decoding of the second instruction and generates second control signals. The second control signals include second resource control signals, second address generation control signals, and a second validity signal indicative of the validity of the second instruction in the second position.Type: GrantFiled: October 1, 1999Date of Patent: May 25, 2004Assignee: Texas Instruments IncorporatedInventors: Karim Djafarian, Gilbert Laurenti, Vincent Gillet
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Patent number: 6681319Abstract: A processing engine 10 includes an instruction buffer 502 operable to buffer single and compound instructions pending execution. A decode mechanism is configured to decode instructions from the instruction buffer. The decode mechanism is arranged to respond to a predetermined tag in a tag field of an instruction, which predetermined tag is representative of the instruction being a compound instruction formed from separate programmed memory instructions. The decode mechanism is operable in response to the predetermined tag to decode at least first data flow control for a first programmed instruction and second data flow control for a second programmed instruction. The use of compound instructions enables effective use of the bandwidth available within the processing engine. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions.Type: GrantFiled: October 1, 1999Date of Patent: January 20, 2004Assignee: Texas Instruments IncorporatedInventors: Karim Djafarian, Gilbert Laurenti, Herve Catan, Vincent Gillet
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Patent number: 6658578Abstract: A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address/data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor.Type: GrantFiled: October 1, 1999Date of Patent: December 2, 2003Assignee: Texas Instruments IncorporatedInventors: Gilbert Laurenti, Jean-Pierre Giacalone, Emmanuel Ego, Anne Lombardot, Francois Theodorou, Gael Clave, Yves Masse, Karim Djafarian, Armelle Laine, Jean-Louis Tardieux, Eric Ponsot, Herve Catan, Vincent Gillet, Mark Buser, Jean-Marc Bachot, Eric Badi, N. M. Ganesh, Walter A. Jackson, Jack Rosenzweig, Shigeshi Abiko, Douglas E. Deao, Frederic Nidegger, Marc Couvrat, Alain Boyadjian, Laurent Ichard, David Russell
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Patent number: 6557097Abstract: A processing engine 10 provides computation of an output vector as a linear combination of N input vectors with N coefficients in an efficient manner. The processing engine includes a coefficient register 940 for holding a representation of each of N coefficients of a first input vector. A test unit 950 is provided for testing selected parts (e.g. bits) of the coefficient register for respective coefficient representations. An arithmetic unit 970 computes respective coordinates of an output vector by selective addition/subtraction of coordinates of a second input vector dependent on results of the coefficient representation tests. Power consumption can be kept low due to the use of a coefficient test operation in parallel with an ALU operation.Type: GrantFiled: October 1, 1999Date of Patent: April 29, 2003Assignee: Texas Instruments IncorporatedInventors: Gael Clave, Karim Djafarian, Gilbert Laurenti
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Publication number: 20030074543Abstract: A processing engine 10 for executing instructions in parallel comprises an instruction buffer 600 for holding at least two instructions, with the first instruction 602 in a first position and the second instruction 604 in a second position. A first decoder 612 provides decoding of the first instruction and generates first control signals. The first control signals include first resource control signals, first address generation control signals, and a first validity signal indicative of the validity of the first instruction in the first position. A second decoder 614 provides decoding of the second instruction and generates second control signals. The second control signals include second resource control signals, second address generation control signals, and a second validity signal indicative of the validity of the second instruction in the second position.Type: ApplicationFiled: October 1, 1999Publication date: April 17, 2003Inventors: Karim Djafarian, Gilbert Laurenti, Vincent Gillett
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Patent number: 6363470Abstract: Data processing apparatus 10 supporting circular buffers CB includes address storage ARx for holding a virtual buffer index and offset storage BOFxx for holding an offset address. Circular buffer management logic 802 is configured to be operable to apply a modifier to a virtual buffer index held in the address storage to derive a modified virtual buffer index and to apply a buffer offset held in the offset storage to the modified virtual buffer index to derive a physical address for addressing a circular buffer. By employing virtual addressing to a buffer index for a circular buffer management, it is possible to make efficient use of memory resources. One or more circular buffers can be located contiguously with respect to each other and/or other data in memory, avoiding fragmentation of the memory. The buffer index forms a pointer for the circular buffer.Type: GrantFiled: October 1, 1999Date of Patent: March 26, 2002Assignee: Texas Instruments IncorporatedInventors: Gilbert Laurenti, Karim Djafarian, Herve Catan