Abstract: An IC, comprising a first rail supply, a second rail supply, an external pad coupled to one of the first rail supply and the second rail supply, and an ESD protection circuit coupled to the external pad. The ESD protection circuit includes a slew rate detector coupled to the external pad, an amplifier coupled to an output of the slew rate detector, a one-shot coupled to an output of the amplifier, and a clamp circuit coupled an output of the one-shot.

Abstract: An overvoltage protection circuit includes an input terminal, an output terminal, a clamp transistor, and a selector circuit. The clamp transistor is configured to control current flow between the input terminal and the output terminal. The clamp transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the output terminal. The selector circuit is configured to control a resistance of the clamp transistor based on a voltage at the input terminal. The selector circuit includes a first terminal coupled to the first terminal of the clamp transistor, a second terminal coupled to the second terminal of the clamp transistor, and a third terminal coupled to a third terminal of the clamp transistor.

Abstract: An electronic circuit includes an electronic device, an input/output terminal, and a protection device. The electronic device includes a signal terminal to receive an input signal. The input/output terminal is configured to receive the input signal from a source external to the electronic circuit. The protection device is coupled to the electronic device and to the input/output terminal. The protection device is configured to protect the electronic device from voltage of the input signal exceeding a threshold. The protection device includes a first semiconductor region, a first contact, and a second contact. The first contact connects the first semiconductor region to the input/output terminal. The second contact connects the first semiconductor region to the signal terminal of the electronic device.

Abstract: A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.

Abstract: An overvoltage protection circuit includes an input terminal, an output terminal, a clamp transistor, and a selector circuit. The clamp transistor is configured to control current flow between the input terminal and the output terminal. The clamp transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the output terminal. The selector circuit is configured to control a resistance of the clamp transistor based on a voltage at the input terminal. The selector circuit includes a first terminal coupled to the first terminal of the clamp transistor, a second terminal coupled to the second terminal of the clamp transistor, and a third terminal coupled to a third terminal of the clamp transistor.

Abstract: An electrostatic discharge (ESD) protection circuit includes a snapback ESD protection device and an ESD tail current clamp circuit. The snapback ESD protection device is configured to shunt current of an ESD event to a voltage reference. The ESD tail current clamp circuit is connected in parallel with the snapback ESD protection device. The ESD tail current clamp circuit is configured to shunt tail current of the ESD event to the voltage reference while the snapback ESD protection device is disabled.

Abstract: An electronic circuit includes an electronic device, an input/output terminal, and a protection device. The electronic device includes a signal terminal to receive an input signal. The input/output terminal is configured to receive the input signal from a source external to the electronic circuit. The protection device is coupled to the electronic device and to the input/output terminal. The protection device is configured to protect the electronic device from voltage of the input signal exceeding a threshold. The protection device includes a first semiconductor region, a first contact, and a second contact. The first contact connects the first semiconductor region to the input/output terminal. The second contact connects the first semiconductor region to the signal terminal of the electronic device.

Abstract: An electronic circuit includes an electronic device, an input/output terminal, and a protection device. The electronic device includes a signal terminal to receive an input signal. The input/output terminal is configured to receive the input signal from a source external to the electronic circuit. The protection device is coupled to the electronic device and to the input/output terminal. The protection device is configured to protect the electronic device from voltage of the input signal exceeding a threshold. The protection device includes a first semiconductor region, a first contact, and a second contact. The first contact connects the first semiconductor region to the input/output terminal. The second contact connects the first semiconductor region to the signal terminal of the electronic device.

Abstract: A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.

Abstract: A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.

Abstract: An electrostatic discharge (ESD) protection circuit includes a snapback ESD protection device and an ESD tail current clamp circuit. The snapback ESD protection device is configured to shunt current of an ESD event to a voltage reference. The ESD tail current clamp circuit is connected in parallel with the snapback ESD protection device. The ESD tail current clamp circuit is configured to shunt tail current of the ESD event to the voltage reference while the snapback ESD protection device is disabled.

Abstract: An electronic circuit includes an electronic device, an input/output terminal, and a protection device. The electronic device includes a signal terminal to receive an input signal. The input/output terminal is configured to receive the input signal from a source external to the electronic circuit. The protection device is coupled to the electronic device and to the input/output terminal. The protection device is configured to protect the electronic device from voltage of the input signal exceeding a threshold. The protection device includes a first semiconductor region, a first contact, and a second contact. The first contact connects the first semiconductor region to the input/output terminal. The second contact connects the first semiconductor region to the signal terminal of the electronic device.

Abstract: A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.

Abstract: A method and an apparatus for transmitting information contained in a transmission signal via at least one channel includes a number of processing steps at the transmitter end. At least one pulse sequence with at least one pulse is produced as stipulated by the transmission signal. The pulse sequence is output to the at least one channel. The channel is monitored for the presence of an interference signal. If an interference signal is detected on the channel, the pulse sequence is repeated.

Abstract: A receiver circuit contains first and second inputs for feeding in first and second input signals, and an output generating an output signal dependent on the input signals. A detector circuit has a first and second signal detectors connected to the first and second inputs, respectively. The signal detectors compare amplitudes of the input signals in each case with a detection threshold and in each case provide a detector output signal. The signal detectors each have a control input for setting the detection threshold, and the control input of the first signal detector is coupled to an output of the second signal detector and the control input of the second signal detector is coupled to an output of the first signal detector. A signal processing circuit receives the detector output signals and generates the output signal according to the detector output signals.

Abstract: A method and an apparatus for transmitting information contained in a transmission signal via at least one channel includes a number of processing steps at the transmitter end. At least one pulse sequence with at least one pulse is produced as stipulated by the transmission signal. The pulse sequence is output to the at least one channel. The channel is monitored for the presence of an interference signal. If an interference signal is detected on the channel, the pulse sequence is repeated.

Abstract: The invention relates to a semiconductor component having a coreless first transformer (71, 72) which comprises a first (71) and a second (72) planar winding, is arranged on a semiconductor body 9 and is surrounded in the lateral direction by a protective ring (1, 2). The protective ring (1, 2) has metal portions (1a-1d), of which the top metal portion (1a) is further apart of the first planar winding (71) in the lateral direction than the protective ring (1b) which is second from top.

Abstract: A method and an apparatus for transmitting information contained in a transmission signal via at least one channel includes a number of processing steps at the transmitter end. At least one pulse sequence with at least one pulse is produced as stipulated by the transmission signal. The pulse sequence is output to the at least one channel. The channel is monitored for the presence of an interference signal. If an interference signal is detected on the channel, the pulse sequence is repeated.

Abstract: A method for transmitting a digital data word, and an apparatus for carrying out the method, include the following processing steps: First, the data word is converted into a first serial differential data sequence which contains the information in at least one initialization bit and in the data bits of the data word in time with a clock signal. The data word is also converted into a second serial differential data sequence which contains the information in at least one initialization bit and in the data bits of an inverted data word, obtained by inverting the data word, in time with the clock signal. Next, the first differential data sequence is transmitted via a first data channel, and the second differential data sequence is transmitted via a second data channel.

Abstract: The invention relates to a receiver arrangement for a push-pull transmission method. First and second signal detectors, to which a first input signal is fed provide first and second detector signals depending on a comparison of the first input signal with a detector threshold. Third and fourth signal detectors, to which a second input signal is fed provide third and fourth detector signals depending on a comparison of the second input signal with a detector threshold. The first and third detector signals are respectively fed to a data input of a first and second buffer store. The second and fourth detector signals are respectively fed to a reset input of the first and second buffer store. The first and second buffer store are designed for buffer-storing signal pulses contained in the first and second detector signals and forwarding them to a respective output for subsequent further processing in time-delayed fashion after a first delay duration.