Abstract: A data retention operation is performed in a non-volatile memory in response to detection of a triggering event. The data retention operation includes updating a value of a write parameter of the non-volatile memory and storing into the non-volatile memory at least one copy of contents of a boot portion of the non-volatile memory using the updated value of the write parameter. The updated value of the write parameter increases retention of stored data during extended periods of inactivity at the non-volatile memory.

Abstract: A data retention operation is performed in a non-volatile memory in response to detection of a triggering event. The data retention operation includes updating a value of a write parameter of the non-volatile memory and storing into the non-volatile memory at least one copy of contents of a boot portion of the non-volatile memory using the updated value of the write parameter. The updated value of the write parameter increases retention of stored data during extended periods of inactivity at the non-volatile memory.

Abstract: A memory controller interface, mobile device and method are provided. The memory controller interface can allow a processor designed and configured to operate with NOR flash and static random access memory SRAM devices to instead operate using NAND flash and synchronous dynamic random access memory SDRAM. The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed by the processor as though it were accessing data from NOR flash/SRAM. Sectors containing data required by the processor are read out of NAND flash and written into SDRAM, where the data can be randomly accessed by the processor. Boot code is stored in memory accessible to the processor and is read out of the memory for execution. The boot code is scanned for a predetermined signature, and if the predetermined signature is found, a portion of the memory is write-protected.

Abstract: A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and SRAM memory devices to instead operate using NAND flash and SDRAM. The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed by the processor as though it were accessing data from NOR flash/SRAM. Sectors containing data required by the processor are read out of NAND flash and written into SDRAM, where the data can be randomly accessed by the processor.

Abstract: A system and method for automatically saving the contents of volatile memory in a data processing device on power failure. A secondary power supply is provided, which upon failure of the primary power supply supplies power long enough for all modified information stored in volatile memory to be written to a non-volatile memory device such as NAND flash in an AutoSave procedure. In the preferred embodiment modified sectors in volatile memory are flagged, and only modified sectors with a directory list are written to non-volatile memory during the AutoSave procedure.

Abstract: A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and static random access memory (SRAM) memory devices to instead operate using NAND flash and synchronous dynamic random access memory (SDRAM). The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed by the processor as though it were accessing data from NOR flash/SRAM. Sectors containing data required by the processor are read out of NAND flash and written into SDRAM, where the data can be randomly accessed by the processor.