Abstract: A data storage device and method for enhanced recovery through data storage device discrete-component-hardware-reset are provided. In one embodiment, the data storage device determines that a subset of a plurality of memory dies is non-responsive, sends a request to a host to accept longer delays associated with the subset of the plurality of memory dies, power-cycles the subset of the plurality of memory dies, and then informs the host that the latency associated with those dies has been restored to normal latency or that the subset of the plurality of memory dies are inactive (in case of unsuccessful recovery). Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: During data storage device operation, data of multiple blocks of a non-volatile memory device, logically grouped as a jumboblock, may be protected by an exclusive or (XOR) signature, where the XOR signature may be used to recover data of a block of the multiple blocks. During a recovery/relocation operation, data of the jumboblock is read from the non-volatile memory device during the recovery of the lost data and again when the data is relocated. However, because the data read during data storage device operation is temporarily stored in a volatile memory device, the controller utilizes the relevant data stored in the volatile memory device and the data stored in the non-volatile memory device to recover corrupted data. Thus, the amount of reads from the non-volatile memory device decreases due to the relevant data is read from the volatile memory device, which may improve data storage device performance.

Abstract: Detecting the removal of a data storage device from a storage system involves first determining that a shorter pin of an electrical connector of a storage device is disconnected from a mating electrical connector, such as by sensing a voltage drop on that pin, then determining at a later time that a longer pin of the connector is disconnected from the mating connector. Responsive to determining that the longer pin was disconnected after a predetermined period of time after the shorter pin, a conclusion may be made that the storage device has been removed from the system as opposed to being subject to a simple device power aberration. Thus, responsive data destruction action(s) may be taken to render the data stored on the device inaccessible to the attacker thereby protecting the device even after the device is removed from the storage system.

Abstract: A data storage device and method for enhanced recovery through data storage device discrete-component-hardware-reset are provided. In one embodiment, the data storage device determines that a subset of a plurality of memory dies is non-responsive, sends a request to a host to accept longer delays associated with the subset of the plurality of memory dies, power-cycles the subset of the plurality of memory dies, and then informs the host that the latency associated with those dies has been restored to normal latency or that the subset of the plurality of memory dies are inactive (in case of unsuccessful recovery). Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: The present disclosure generally relates to achieving an acceptable uncorrectable bit error rate (UBER) using a dual temporary data protecting approach and a small SLC cache by adding a temporary XOR protection to zone-groups rather than storing another copy of the zone within the drive. The parity data can be stored with the user data (e.g., as part of the zone-group, effectively increasing zone-group size by 1) or in a separate location, e.g., in an SLC block or another separate MLC block.

Abstract: The present disclosure generally relates to creating and recalibrating zone groups. Rather than having a fixed zone group size, the zone group size can be dynamic where the data storage device provides a range of zone group sizes to a host device. Based upon block availability and host device commands, new zone groups may be formed of different sizes within the provided range. If there is an insufficient number of blocks available to create a zone group with a size within the provided range, the data storage device can recalibrate. The insufficient number of blocks may be due to bad blocks and/or fragmentation. To obtain more blocks, garbage collection can occur and/or the data storage device can request the host device to release some blocks. The dynamic zone group creation and recalibration ensures more efficient operation of the data storage device.

Abstract: The present disclosure generally relates to efficiently relocating data within a data storage device. By implementing an error correction code (ECC) module in a complementary metal oxide semiconductor (CMOS) chip for each memory die within a memory array of a memory device, the data can be relocated more efficiently. The ECC decodes the codewords at the memory die. The metadata is then extracted from the decoded codewords and transferred to a controller of the data storage device. A flash translation layer (FTL) module at the controller then checks whether the data is valid by comparing the received metadata to FTL tables. If the metadata indicates the data is valid, then the data is relocated.

Abstract: A data storage device including a non-volatile memory device including one or more non-volatile memory sets and one or more endurance groups. Each of the endurance groups includes at least one of the non-volatile memory sets. The data storage device includes a controller coupled to the non-volatile memory device. The controller is configured to receive a pending command message from a host interface, where the received pending command message includes a command configured to be executed by a first endurance group of the number of endurance groups. The controller is further configured to determine an assigned command slot for storing the command, where the assigned command slot is selected form one of a private command slot pool associated with the first endurance group or a shared command slot pool, fetch the command from the host device, and store the fetched command in the assigned command slot.

Abstract: A host sends a storage system a command to read data from a memory and then a command to write the data back to the memory to defragment the data. The host sends flags along with the commands. The flag sent with the read command causes the storage system to take a snapshot of the logical-to-physical address map relevant to the data. The flag sent with the write command causes the storage system to compare the snapshot with the current version of the logical-to-physical address map and write the data back to the memory only if there is a match.

Abstract: The present disclosure generally relates to improved foggy-fine programming. Rather than initially writing to SLC and then later performing a foggy write to QLC with the data read from SLC and then a fine write to QLC with data re-read from SLC, the foggy write to QLC can be performed in parallel to the initial writing to SLC using the same buffer. Once the foggy write to QLC has completed, and the writing to SLC has also completed, the data buffer can be released. The data written in SLC is then be read from SLC and passes through a relocation buffer for the first and only time to then be written using fine programming to QLC. Thus, the data only passes through the relocation buffer one time and the relocation buffer can be freed to usage after only one pass of the data therethrough.

Abstract: A storage system determines a memory fragmentation level for each of a plurality of logical block address ranges. The memory fragmentation level for a given logical block address range is determined according to the number of memory senses required to read that logical block address range in its current state of fragmentation and the number of memory senses required to read that logical block address range assuming no fragmentation. The memory fragmentation level correlates to the sequential read performance for that logical block address range in that an increase in the memory fragmentation level results in a decrease in sequential read performance.

Abstract: For a non-volatile memory system with a multi-plane memory die having a large block size, to be able to more readily accommodate zone-based host data using zones that are of a smaller size that the block size on the memory, the memory system assigns data from different zones to different subsets of the planes of a common memory die. The memory system is configured to accumulate the data from the different zones into different write queues and then assemble the data from the different write zones into pages or partial pages of data that can be simultaneously programmed into memory cells connected to different word lines that are in different sub-blocks of different blocks in the corresponding assigned planes of the die.

Abstract: Data storage devices, such as solid state drives (SSDs), are disclosed. A read threshold calibration operation is utilized to generate a calibrated read threshold for one or more voltage states of a cell of a MLC memory. A single-level cell (SLC) read is then executed to sense the ratio of bit values at the read thresholds of the voltage states, where SLC read refers to reading at a single read threshold, rather than to the cell type. The sensing results in a binary page with certain statistics of 1's and 0's. The ratio of 1's (or 0's) in the binary page is used to determine a deviation from the expected ratio, where the deviation is used to adjust the calibrated read threshold to match the voltage states of the MLC memory.

Abstract: Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

Abstract: A host sends a storage system a command to read data from a memory and then a command to write the data back to the memory to defragment the data. The host sends flags along with the commands. The flag sent with the read command causes the storage system to take a snapshot of the logical-to-physical address map relevant to the data. The flag sent with the write command causes the storage system to compare the snapshot with the current version of the logical-to-physical address map and write the data back to the memory only if there is a match.

Abstract: A storage system determines a memory fragmentation level for each of a plurality of logical block address ranges. The memory fragmentation level for a given logical block address range is determined according to the number of memory senses required to read that logical block address range in its current state of fragmentation and the number of memory senses required to read that logical block address range assuming no fragmentation. The memory fragmentation level correlates to the sequential read performance for that logical block address range in that an increase in the memory fragmentation level results in a decrease in sequential read performance.

Abstract: Effective use of cyclic redundancy check (CRC) signatures is achieved where each sector of a flash management unit (FMU) has a distinct CRC signature. The CRC signatures are XORed together to create a total CRC signature for the FMU. When a host device updates a single sector of the FMU, the CRC signature for the updated single sector can be changed by removing the old CRC signature corresponding to the single sector and replacing the old CRC signature with a new CRC signature corresponding to the updated single sector. The old CRC signature is XORed from the total CRC signature and then the new CRC signature is XORed with the remaining CRC signatures to create a new total CRC signature. In so doing, data integrity is ensured.

Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.

Abstract: A method and apparatus for video processing on a data storage device. A chip bound architecture includes a CMOS coupled to one or more NAND die, the CMOS including one or more processors, memories, and error correction code (ECC) engines capable of processing video data. According to certain embodiments, macroblocks are correlated between two I-frames, including motion vectors to define different locations of correlated macroblocks. A P-frame may be determined from a previous I-frame and its correlated macroblocks and motion vectors, while a B-frame may be determined from two or more adjacent I-frames with concomitant macroblocks and motion vectors, as well as P-frames associated with an adjacent I-frame.

Abstract: A method and apparatus for dynamic controller buffer management is disclosed. According to certain embodiments, responsive to commands received from a host, a controller may adjust one or more partitions of a controller buffer memory to adjust the size of different types of buffer memory. In some embodiments, preset buffer memory configurations may be applied to the buffer memory to adjust buffer memory allocation based on the current workload. By way of example, when sequential reads are detected, a TRAM buffer size may be increased to provide additional RLA buffers, at the expense of XRAM and/or L2P buffer size. Where operations involving SLC memory is detected, allocation of buffer memory parity buffers of XRAM may be decreased, to provide additional buffer space to L2P.