Abstract: Determining simulation test coverage for a design of an electronic circuit, where graph-based verification tools are used to verify functional correctness of said design. A test coverage is determined from specified coverage points, and hardware test coverage is measured based on the occurrence of selected events. A specification for simulation test scenarios, and a hardware design language specification for the design comprising hardware events are provided. A list of event groups belonging to one simulation test scenario is created. For each group a temporal property coverage checker in the simulation model is generated that comprises a switch to enable or disable it.

Abstract: A method and system for increasing performance when modeling random latch values are provided. The system including a power management logic that provides a power signal (VDD) that includes a high portion and a low portion, a transformation logic that receives the VDD from the power management logic, generates a updated signal (VDD2) based on the VDD, and outputs the updated signal (VDD2), wherein the VDD2 includes a low portion that extends one cycle, and a latch connected to transformation logic, wherein the latch receives VDD2.

Abstract: A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

Abstract: The present invention provides a system, apparatus, and method for detecting and resolving read-after-write hazards encountered in processors following the dispatch of instructions requiring one or more implicit reads in a processor.

Abstract: A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

Abstract: The present invention provides a new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

Abstract: The present invention provides a new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

Abstract: The present invention relates to hardware design and simulation thereof. In particular, it relates to a method and system for verifying hardware designs. It is basically proposed to provide a plurality of instruments, i.e., a kind of testcase language, which is able to simplify the hardware verification work. Each of the language elements contributes specifically to the general aim of the present invention, i.e., to improve the management of test cases and their execution. For example, a construct language element is provided which is able to be filled up with technical information about one or more hardware logic functions, and which checks their functionality by its own, returning an error value. Thus, the advantage results that due to the systematic management of testcases an efficient testcase generation and execution can be performed.