Patents by Inventor Karl D. Schuh

Karl D. Schuh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200319827
    Abstract: Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 8, 2020
    Inventors: Gianni Stephen Alsasua, Karl D. Schuh, Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Sampath Ratnam, Harish Reddy Singidi, Renato Padilla, JR.
  • Patent number: 10795828
    Abstract: A computer device reads an indicator from a configuration file that identifies a granularity of units of data at which to track validity. The granularity is one of a plurality of granularities ranging from one unit of data to many units of data. The computer device generates a machine-readable file configured to cause a processing device of a memory system to track validity at the identified granularity using a plurality of data validity counters with each data validity counter in the plurality of data validity counters tracking validity of a group of units of data at the identified granularity. The computer device transfers the machine-readable file to a memory of the memory system.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: October 6, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Boon Leong Yeap, Karl D. Schuh
  • Publication number: 20200293476
    Abstract: A first operation identifier is assigned to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier. It is determined whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier. A latest flag is updated to indicate that the first entry is a latest operation directed to an address (1) in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, or (2) in response to determining to determining that the current operation does not collide with a prior operation.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 17, 2020
    Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
  • Publication number: 20200285416
    Abstract: A program operation is executed on a memory sub-system. During execution of the program operation, a request to execute a read operation on the memory sub-system is received. In response to receiving the request, a program suspend operation to suspend the program operation is executed. The read operation is executed on the memory sub-system in response to a completion of the program suspend operation. In response to completion of the read operation, a program resume operation is executed. A program suspend delay period is established following execution of the program resume operation during which a subsequent read operation is stored in a queue.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Inventors: Jiangang Wu, Sampath K. Ratnam, Yang Zhang, Guang Chang Ye, Kishore Kumar Muchherla, Hong Lu, Karl D. Schuh, Vamsi Pavan Rayaprolu
  • Publication number: 20200278927
    Abstract: Systems and methods for storing and validating namespace metadata are disclosed. An exemplary system includes a memory component and a processing device receiving a first read instruction from a host process. The first read instruction includes a namespace offset. A first logical address is generated by combining a namespace identifier for the namespace assigned to the host process and the namespace offset. The first logical address is translated into a first physical address using a plurality of hierarchical tables. A second read instruction, which includes the first physical address and the first logical address, is generated. The second read instruction is sent to a memory component. The memory component validates the translation of the first logical address by comparing the first logical address in the second read instruction to metadata associated with data to be read at the first physical address.
    Type: Application
    Filed: May 15, 2020
    Publication date: September 3, 2020
    Inventors: Byron D. Harris, Karl D. Schuh
  • Patent number: 10761978
    Abstract: Exemplary methods, apparatuses, and systems include receiving an instruction to atomically write data to a memory component. A plurality of write commands for the first data are generated, including an end of atom indicator. The first plurality of write commands are sent to the memory component while accumulating a plurality of translation table updates corresponding to the write commands One or more translation tables are updated with the plurality of translation table updates in response to determining that the final write command has been successfully sent to the memory component.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: September 1, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Nathan Jared Hughes, Karl D. Schuh, Tom Geukens
  • Publication number: 20200264984
    Abstract: An entry is read from a first memory component, the entry associated with a first logical address. The first entry includes a first physical address to a segment of a logical-to-physical address map in a second memory component and an indication of whether the segment of the logical-to-physical address map is stored in the first memory component. The segment of the logical-to-physical address map includes a second entry associated with the first logical address. A second physical address is written to the second entry in the first memory component based on a determination from the indication that the segment of the logical-to-physical address map is stored in the first memory component.
    Type: Application
    Filed: September 3, 2019
    Publication date: August 20, 2020
    Inventors: Lyle E. ADAMS, Sheng BI, Karl D. SCHUH, Pushpa SEETAMRAJU, Dan Z. TUPY, Yongcai XU
  • Patent number: 10719271
    Abstract: Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: July 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gianni Stephen Alsasua, Karl D. Schuh, Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Sampath Ratnam, Harish Reddy Singidi, Renato Padilla, Jr.
  • Patent number: 10705996
    Abstract: A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 7, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
  • Patent number: 10691592
    Abstract: Systems and methods for storing and validating namespace metadata are disclosed. An exemplary system includes a memory component and a processing device identifying a namespace identifier associated with a first write instruction from a host process and combining the namespace identifier with a namespace offset included in the first write instruction to form a logical address. The logical address is translated into a physical address and included in a second write instruction along with data to be written and the physical address. The second write instruction is sent to a memory component causing the data to be written at the physical address, and the logical address to be stored as metadata associated with the data. The logical address may be translated using a namespace table and one or more translation tables, where the namespace table has entries including a starting location and size of a namespace in a translation table.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 23, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Byron D. Harris, Karl D. Schuh
  • Publication number: 20200192844
    Abstract: A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.
    Type: Application
    Filed: November 25, 2019
    Publication date: June 18, 2020
    Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
  • Publication number: 20200174693
    Abstract: Each of a multiple cursors is assigned a respective generator of multiple generators. The cursors are used to perform an operation on a set of logical unit numbers (LUN) associated with memory devices. Multiple sequences of LUNs are identified based on the generators. Each of the cursors is associated with one of the sequences of LUNs. The operation on the set of LUNs associated with the memory devices is performed using the sequences of LUNs. The operation on the set of LUNs is performed in an order provided by the sequences of LUNs to reduce a probability of collision by the cursors in the performance of the operation.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 4, 2020
    Inventors: Daniel A. Boals, Karl D. Schuh, Byron D. Harris
  • Publication number: 20200174935
    Abstract: A controller selects a redundancy context for eviction in response to a request for a redundancy context. The redundancy context includes buffer data and an identifier. The redundancy context is evicted by instructing a redundancy component to send the buffer data and identifier to a memory component to store in a buffer as an evicted context. The controller instructs the memory component to provide the evicted context for storage in a controller buffer. A new redundancy context is allocated to the requester following the eviction.
    Type: Application
    Filed: December 3, 2018
    Publication date: June 4, 2020
    Inventors: James P. Crowley, Yuriy Pavlenko, Karl D. Schuh
  • Publication number: 20200159446
    Abstract: Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Gianni Stephen Alsasua, Karl D. Schuh, Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Sampath Ratnam, Harish Reddy Singidi, Renato Padilla, JR.
  • Publication number: 20200133833
    Abstract: Exemplary methods, apparatuses, and systems include receiving an instruction to atomically write data to a memory component. A plurality of write commands for the first data are generated, including an end of atom indicator. The first plurality of write commands are sent to the memory component while accumulating a plurality of translation table updates corresponding to the write commands One or more translation tables are updated with the plurality of translation table updates in response to determining that the final write command has been successfully sent to the memory component.
    Type: Application
    Filed: October 25, 2018
    Publication date: April 30, 2020
    Inventors: Nathan Jared Hughes, Karl D. Schuh, Tom Geukens
  • Publication number: 20200133849
    Abstract: Systems and methods for storing and validating namespace metadata are disclosed. An exemplary system includes a memory component and a processing device identifying a namespace identifier associated with a first write instruction from a host process and combining the namespace identifier with a namespace offset included in the first write instruction to form a logical address. The logical address is translated into a physical address and included in a second write instruction along with data to be written and the physical address. The second write instruction is sent to a memory component causing the data to be written at the physical address, and the logical address to be stored as metadata associated with the data. The logical address may be translated using a namespace table and one or more translation tables, where the namespace table has entries including a starting location and size of a namespace in a translation table.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Inventors: Byron D. Harris, Karl D. Schuh
  • Publication number: 20200104251
    Abstract: A portion of a logical block address to physical block address (“L2P”) translation map may be identified. A last snapshot of the portion of the L2P translation map may be identified. One or more write operations may be determined, where the write operations are associated with logical block addresses of the portion of the L2P translation map. The write operations may have been performed after the last snapshot of the portion of the L2P translation map was stored. An address on the portion of the L2P translation map may be updated by a processing device based on the determined one or more write operations and the last snapshot of the portion of the L2P translation map.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Daniel A. Boals, Byron D. Harris, Karl D. Schuh, Amy L. Wohlschlegel
  • Publication number: 20200050556
    Abstract: A computer device reads an indicator from a configuration file that identifies a granularity of units of data at which to track validity. The granularity is one of a plurality of granularities ranging from one unit of data to many units of data. The computer device generates a machine-readable file configured to cause a processing device of a memory system to track validity at the identified granularity using a plurality of data validity counters with each data validity counter in the plurality of data validity counters tracking validity of a group of units of data at the identified granularity. The computer device transfers the machine-readable file to a memory of the memory system.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Boon Leong Yeap, Karl D. Schuh
  • Patent number: 10521383
    Abstract: A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 31, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
  • Publication number: 20190171576
    Abstract: An offset can be determined based on a characteristic of a memory system associated with a system block. The system block corresponds to logical blocks. A first group of physical blocks of the memory system can be assigned to a group of the plurality of logical blocks of the system block. A second group of physical blocks of the memory system can be identified at a location that is based on the offset and the first group of physical blocks. Furthermore, the second group of physical blocks of the memory system can be assigned to another group of the plurality of logical blocks associated with the system block. Data can be stored by using the system block with the first group and second group of physical blocks.
    Type: Application
    Filed: November 14, 2018
    Publication date: June 6, 2019
    Inventors: Ashutosh Malshe, Karl D. Schuh