Abstract: The present invention relates to a scribing method for wafers (11), wherein a defined beam (12) is directed onto the wafer (11) by means of a beam generator means (10) so as to remove some wafer material from a wafer region. The invention also relates to a wafer-scribing device including a wafer mount (31) and a beam generator means (10) by means of which at least one defined beam can be directed onto the wafer (11). The inventive method is distinguished by the by the further step of generating a first radiation pulse having a predeterminable energy density and used to create a comparatively deep pit (18) in the wafer (11). The inventive wafer scribing means is distinguished by the provision that a radiation pulse can be generated by means of which a comparatively deep pit (18) can be created in the wafer (11).

Abstract: A lithography and etching method for forming an alignment mark (104) and at least one device feature (such as a shallow trench 105) on a wafer (99) is provided. The etching process (18) comprises: a first etching step (1811) for pre-defining at least one alignment mark (103) and a second etching step (1812) for defining desired semiconductor device patterns (such as a shallow trench 105) on said wafer surface and completing said at least one alignment mark (104).

Abstract: An arrangement for transferring a pattern from a mask (100) onto a wafer is provided. A product area (110) of the mask (100) is at least partly surrounded by a frame (112) having an alignment mark area (114). In order to avoid the need to produce a specific mask set for different alignment styles, the mask (100) and the frame (112) are designed as being separate units. Further, methods for transferring a pattern from a mask to a wafer are provided that employ a frame separated from a product area.

Abstract: A lithography and etching method for forming an alignment mark (104) and at least one device feature (such as a shallow trench 105) on a wafer (99) is provided. The etching process (18) comprises: a first etching step (1811) for pre-defining at least one alignment mark (103) and a second etching step (1812) for defining desired semiconductor device patterns (such as a shallow trench 105) on said wafer surface and completing said at least one alignment mark (104).

Abstract: A method for monitoring a polishing condition of a surface of a wafer in a polishing process is provided, the method comprising providing a wafer (16) to be polished, the wafer (16) having at least one optically distinguishable feature (20) below a transparent or translucent layer (22) to be polished; selecting one or more of the features (20) for monitoring; measuring an optical contrast profile (62; 72; 82; 92) across one or more of the selected features (20); determining the polishing condition of the surface of the wafer (16) on the basis of the measured contrast profile (62; 72; 82; 92); and repeating the measuring the optical contrast profile (62; 72; 82; 92) and determining the polishing condition until a predetermined polishing condition is reached. A method for polishing wafers by a CMP polishing tool and apparatus for monitoring a polishing condition of a surface of a wafer (16) is also provided.

Abstract: A system for monitoring ion implantation processing on a semiconductor wafer (10), comprising a plurality of Faraday cups (12-28, 32) for collecting charge that is not deposited on the wafer (10) during ion implantation processing, means (40) for determining Faraday cups (12-28, 32) that are collecting charge in a particular position of an ion beam (30) relative to the wafer (10) and means (40) for determining the particular ion beam position relative to the wafer (10) on the basis of the Faraday cups (12-28, 32) collecting charge. The present invention further relates to a method of monitoring ion implantation processing.

Abstract: A method for monitoring a polishing condition of a surface of a wafer in a polishing process is provided, the method comprising the steps of providing a wafer (16) to be polished, the wafer (16) having at least one optically distinguishable feature (20) below a transparent or translucent layer (22) to be polished; selecting one or more of said features (20) for monitoring; measuring an optical contrast profile (62; 72; 82; 92) across one or more of said selected features (20); determining the polishing condition of the surface of the wafer (16) on the basis of the measured contrast profile (62; 72; 82; 92); and repeating the steps of measuring the optical contrast profile (62; 72; 82; 92) and determining the polishing condition until a predetermined polishing condition is reached. The invention also provides a method for polishing wafers by a CMP polishing tool and apparatus for monitoring a polishing condition of a surface of a wafer (16) in a polishing process.

Abstract: A processing tool bay within a semiconductor fabrication site, including a plurality of semiconductor processing tools for processing wafers being arranged in two opposite rows. An intrabay transport system for transporting wafer carriers around the process tool bay at least in a vertical plane in front of one of said two rows of semiconductor process tools comprises at least one vehicle for receiving and delivering a wafer carrier to and from any one semiconductor process tool of said plurality of semiconductor process tools, and a vehicle guiding mechanism. The vehicle comprises a circular compartment structure including a plurality of compartments for buffering said wafer carrier between receiving it at a first location and delivering it at a second location. Each compartment is arranged for accommodating one wafer carrier. The compartment structure is rotatable around a symmetry axis of itself for an alignment.

Abstract: An arrangement for transferring a pattern from a mask (100) onto a wafer is provided. A product area (110) of the mask (100) is at least partly surrounded by a frame (112) having an alignment mark area (114). In order to avoid the need to produce a specific mask set for different alignment styles, the mask (100) and the frame (112) are designed as being separate units. Further, methods for transferring a pattern from a mask to a wafer are provided that employ a frame separated from a product area.

Abstract: The present invention relates to a method of cleaning a wafer chuck (10) by an automated system that supplies a solvent to a chuck surface (12), washes the chuck surface (12), and dries the chuck surface (12) by spinning the chuck (10), in one embodiment. In another embodiment, the chuck surface (12) is dried by pulling a vacuum on the chuck surface (12) or flowing a gas on the chuck surface (12). Additionally, a brush can be used to wash the chuck surface (12).

Abstract: The present invention relates to a scribing method for wafers (11), wherein a defined beam (12) is directed onto the wafer (11) by means of a beam generator means (10) so as to remove some wafer material from a wafer region. The invention also relates to a wafer-scribing device including a wafer mount (31) and a beam generator means (10) by means of which at least one defined beam can be directed onto the wafer (11).

Abstract: The present invention generally relates to a method for controlling the temperature of a substantially flat object and to a temperature-controlled chuck comprising a chuck body (20) having an object support side (21) and a back side (22). Said object support side (21) holds a substantially flat object (1) having a front side (2) and a back side (3) on said back side (3) of said object (1). A plurality of temperature sensing elements (4) is distributed on said object support side (1) to measure the temperature distribution of said flat object (1). A plurality of individual temperature influencing elements (6; 8; 9) is distributed on said object support side (21) to face said back side (3) of said flat object (1), each of said temperature influencing elements (6; 8; 9) being arranged to influence the temperature of a partial area of said object's back side (3) as desired.

Abstract: The present invention generally relates to a method for controlling the temperature of a substantially flat object and to a temperature-controlled chuck comprising a chuck body (20) having an object support side (21) and a back side (22). Said object support side (21) holds a substantially flat object (1) having a front side (2) and a back side (3) on said back side (3) of said object (1). A plurality of temperature sensing elements (4) is distributed on said object support side (1) to measure the temperature distribution of said flat object (1). A plurality of individual temperature influencing elements (6; 8; 9) is distributed on said object support side (21) to face said back side (3) of said flat object (1), each of said temperature influencing elements (6; 8; 9) being arranged to influence the temperature of a partial area of said object's back side (3) as desired.

Abstract: A method of removing photoresist (20) from a metal layer (16) formed on a substrate (1) and having a pattern defined by means of a corrosive gas plasma etch. The method consists of etching the resist (20) in an oxygen gas plasma for a period of time and at a sufficiently high temperature to remove all residual corrosive gas absorbed in the photoresist and below the temperature at which the metal beings to flow. An etching time of 3 minutes at 300.degree. C. is typically used.

Abstract: A metal etch processing sequence eliminates the need to use an organic masking layer solvent and etches a portion of an insulating layer after a plasma metal etching step. The etch of the insulating layer is performed with an etching solution that may include 1,2-ethanediol, hydrogen fluoride, and ammonium fluoride. The etching solution etches in a range of 100-900 angstroms of the insulating layer. The etch removes at least 75 percent of the mobile ions within the insulating layer, and should remove at least 95 percent of the mobile ions. The process may be implemented using an acid hood, an acid compatible spray tool, or a puddle processing tool. The process includes many different embodiments that allow the process to be easily integrated into many different existing processing sequences. A similar process may be used with a resist-etch-back processing sequence.

Abstract: A method for etching vias having sloped sidewalls is provided, wherein the vias are formed in an interlayer dielectric formed on top of an interconnect layer using a patterned photoresist film as a mask. A top portion of the via is formed with a wet etch process which isotropically undercuts the masking film thereby creating a sloped sidewall. A bottom portion of the via is formed by a dry etch process comprising the steps of alternating between a number of isotropic mask erosion steps and a number of anisotropic dielectric etch steps, so that the interlayer dielectric exposed to the anisotropic etch by the mask opening is enlarged with each mask erosion step. Thus, a slope is created on the dry etched portion of the via sidewall as well as the wet etched portion of the via sidewall.

Abstract: A process described provides a sloped contact etch. The process has the steps of: etching a substrate then removing the polymer that is produced during the substrate etch. These two steps are alternated until a desired depth is reached. Next, the resist is etched followed by an etch of the substrate. This is then repeated until the required depth is reached. By varying the duration and repetition of the etches, the slope of the etch can be regulated.