Abstract: A video control system, comprises a deflection system having a dimensionally adjustable raster, a circuit for detecting a letterbox video signal source and a circuit for dimensionally controlling the raster of the deflection system responsive to the detecting circuit. The detecting circuit and the control circuit are operable automatically. The detection circuit can comprise a circuit for measuring video luma levels of the video signal source in at least two regions of each video field and a circuit for comparing the luma levels from each of the regions to respective threshold levels. In an alternative, the detection circuit comprises a circuit for comparing respective minimum and maximum luminance values for a plurality of successive video lines, a circuit for storing minimum and maximum luminance values for the plurality of video lines, a circuit for generating gradients indicative of the stored values and a circuit for comparing the gradients to threshold values.

Abstract: A circuit for compressing and expanding video color component data comprises a FIFO line memory and a delay circuit. A timing circuit generates control signals for writing data into the line memory and for reading data from the line memory to compress and expand the data. The delay circuit matches the data compressed or expanded in the FIFO line memory to luminance data which is similarly compressed or expanded. A switching network selectively establishes a first signal path in which the line memory precedes the delay circuit for implementing the data expansion and a second signal path in which the delay circuit precedes the line memory for implementing the data compression. The switching network is controlled according to selected display formats requiring compression or expansion, for example by a microprocessor.

Abstract: A two stage interpolation system provides greater bandwidth for signals compressed and expanded by interpolation, for example video signals displayed in a zoom or enlarged mode. A finite impulse response filter generates from a first signal of digital samples a second signal of digital samples representing signal points between the samples of the first signal. The first signal is delayed, but otherwise substantially unmodified. The second signal and the delayed first signal are interleaved, for example by a multiplexer, to produce a third signal of digital values having a sample density twice that of the first signal. A compensated variable interpolator derives from the third signal a fourth signal of digital samples in which the frequency content of information represented by the first signal has been changed.

Abstract: A circuit for compressing and expanding video data comprises a FIFO line memory and an interpolator. A timing circuit generates control signals for writing data into the line memory and for reading data from the line memory to compress and expand the data. The interpolator smooths the data expanded or to be compressed in the FIFO line memory. A switching network selectively establishes a first signal path in which the line memory precedes the interpolator for implementing the data expansion and a second signal path in which the interpolator precedes the line memory for implementing the data compression. The switching network is controlled according to selected display formats requiring compression or expansion, for example by a microprocessor.

Abstract: A video display control system comprises a display for the video signal, a vertical zoom circuit for generating from the video signal a picture having a vertical height greater than the display, and, a vertical panning circuit for displaying a selected portion of the picture on the display by generating a time delay relative to a vertical synchronizing component of the video signal. A counter and comparator measure the respective durations of successive fields of the video signal and the time delay. A circuit responsive to the comparing means generates a first signal for initiating delayed reset pulses when a field of the video signal and the time delay match in duration. Another circuit generates a second signal for initiating the delayed reset pulses in accordance with the vertical synchronizing component. A gating circuit selects the first initiating signal as an output, if present, and selects the second initiating signal as an output absent detection of the first initiating signal.