Abstract: Invocation language is described that is suitable for controlling a machine to perform a process having concurrent parts. Each concurrent part has an association relationship, a completeness relation, and an invocation expression.

Abstract: An electronic processing element is disclosed for use in a system having a plurality of processing elements. The electronic processing element includes an input instruction memory, an operation unit, and an output instruction memory. The input instruction memory is configured to store and retrieve a plurality of operation codes and, for each operation code, an associated output instruction memory address. The operation unit is configured to generate an output datum defined by at least a selected operation code and an associated input datum. The output instruction memory is configured to receive the output instruction memory address and to retrieve an address for an input instruction memory of a second processing element. Upon selection of an input instruction memory address and presentation of an associated input datum, the processing element generates an output datum in association with a corresponding input instruction memory address of the second processing element.

Abstract: An electronic processing element is disclosed for use in a system having a plurality of processing elements. The electronic processing element includes an input instruction memory, an operation unit, and an output instruction memory. The input instruction memory is configured to store and retrieve a plurality of operation codes and, for each operation code, an associated output instruction memory address. The operation unit is configured to generate an output datum defined by at least a selected operation code and an associated input datum. The output instruction memory is configured to receive the output instruction memory address and to retrieve an address for an input instruction memory of a second processing element. Upon selection of an input instruction memory address and presentation of an associated input datum, the processing element generates an output datum in association with a corresponding input instruction memory address of the second processing element.

Abstract: Invocation language is described that is suitable for controlling a machine to perform a process having concurrent parts. Each concurrent part has an association relationship, a completeness relation, and an invocation expression.

Abstract: A programming language for representing processes as strings of symbols has a syntax delimiting places in a symbol string. A convention associates delimited places in symbol strings. An invocation construct instantiated as an invocation string has at least (i) an invocation destination list of delimited places comprising a complete set of inputs for a process, and (ii) an invocation source list of delimited places comprising a complete set of results for the process.

Abstract: Disclosed is an array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an input cell, an output cell, and a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell. Additional cells are similarly configured. Memory presents configuration instructions to cells in response to a configuration code. Data advances through ranks of the cells. The configuration code advances to memory associated with a rank in tandem with the data.

Abstract: A NULL convention asynchronous register regulates wavefronts of signals through a NULL convention sequential circuit. The asynchronous register receives a control signal from a downstream circuit when the downstream circuit is ready to receive a new wavefront. Wavefronts alternate between meaningful data and NULL. The asynchronous register further generates a feedback signal to upstream circuits so that upstream circuits generate a wavefront when the sequential circuit is ready to receive the wavefront. Asynchronous registers can be used to create a variety of architectures, and to store data, as in a sequential circuit (state machine).

Abstract: An electronic data processing circuit is disclosed having at least an instruction memory, an instruction decoder; and a slot structure. The slot structure is characterized by a plurality of slots. Each slot has at least: (1) an address register (2) a data register, (4) a function register, and (3) a monitoring circuit. Each slot asynchronously performs operations defined by the information content of their respective address register, data register and function register when complete information is present.

Abstract: A live video insertion system efficiently places static or dynamic images into a live broadcast. The system initially identifies natural landmarks within the video scene that can be automatically identified and tracked as the field of view of the camera pans and zooms across the scene. The locations of the landmarks are mathematically modeled and stored as a constellation of locations on a mathematical grid. An arbitrary reference point, preferably not necessarily coincident with a selected natural landmark, is located within or without of the grid and used as an origin for the purpose of inserting the static or dynamic image within the field of view of the camera. For static images, it is frequently desirable to place an edge or border of the image to be inserted on the reference point. For dynamic insertions, the distance between the reference point and the inserted dynamic image is automatically changed from frame to frame in order to make the image appear as though it's translating or changing, or both.

Abstract: A NULL convention threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL.

Abstract: A NULL convention asynchronous register regulates wavefronts of signals through a NULL convention sequential circuit. The asynchronous register receives a control signal from a downstream circuit when the downstream circuit is ready to receive a new wavefront. Wavefronts alternate between meaningful data and NULL. The asynchronous register further generates a feedback signal to upstream circuits so that upstream circuits generate a wavefront when the sequential circuit is ready to receive the wavefront. Asynchronous registers can be used to create a variety of architectures, and to store data, as in a sequential circuit (state machine).