Abstract: A method for analyzing and displaying process states of a technical plant includes enabling simultaneous, coherent assessment and display of relevant process variables of the plant by evaluating relevant process variables with regard to one another through the use of a neural analysis on the basis of self-organizing maps, by making a topology-producing projection of data of the relevant process variables onto a neural map. The current process courses are plotted as trajectories on the map. Evaluation in the sense of a diagnosis can be carried out either visually or in an automated manner.

Abstract: The invention relates to a method for operating recursive filter circuits or analog storage circuits constructed according to the charge coupled device principle and relates to a circuit arrangement for implementing the method, in which method only each respective second stage of a CCD is occupied with a charge representing a sampling value of an analog signal and the respective stages lying between these stages concerned and left empty. Known circuits constructed according to the CCD principle conduct the signal from the output stage of a CCD chain to the input of the CCD loop via an amplifier to which the input signal is supplied at the same time. Thereby, the amplification must very precisely amount to one. An amplifier of the high stability required thereto which is arranged in common with the concerned CCD on a chip cannot be satisfactorily realized.

Abstract: The invention relates to a method for operating recursive filter circuits or analog storage circuits constructed according to the charge coupled device principle and to a circuit arrangement for implementing the method, in which method only each respective second stage a CCD is occupied with a charge representing a sampling value of an analog signal and the respective stages lying between these stages concerned are left empty. Known circuits constructed according to the CCD principle conduct the signal from the output stage of a CCD chain to the input of the CCD loop via an amplifier to which the input signal is supplied at the same time. Thereby, the amplification must very precisely amount to 1. An amplifier of the high stability required for that purpose which is arranged in common with the CCD concerned on a chip cannot be satisfactorily realized.

Abstract: An electronic control system for analog circuits has controllable analogue circuits which can be combined with one another by way of an electronic switching network. The digital states of the individual crosspoints of the switching network can be programmed by way of a common switching network. In addition, circuitry is provided for adjusting the operating parameters of the individual analogue circuits and the adjustment is accomplished through the values for the operating parameters being determined in a parameter memory according to a program. Finally, a synchronization of the functional sequence of the programs present in two memories is provided.

Abstract: A circuit arrangement CHL technique (current hogging logic) includes individual CHL arrangements each having an emitter, control collectors and an output collector and arranged within an epitaxial layer. The individual CHL arrangements are complementary with respect to one another, and arrangement of one conductivity type being directly integrated in the epitaxial layer and the arrangement which is complementary thereto being integrated in a basin in the epitaxial layer, the basin being doped opposite to the epitaxial layer.

Abstract: A semiconductor storage arrangement employing a pair of field-effect transistors which are complementary to one another and connected in series, one of the transistors having the source area thereof connected to the gate area of the second transistor and the gate area of the first transistor being connected to the drain area of the second transistor, the drain area of the first transistor being connected to the source area of the second transistor, in which both transistors are disposed on a common semi-conductor substrate and one of the transistors is a junction field-effect transistor, the gate area of which simultaneously forms the source or drain area of the other transistor.

Abstract: A pair of bipolar transistors are formed in a semiconductor substrate with each transistor having at least one emitter, one base and at least one collector. At least the base is in the form of a doped zone in the substrate. The two base zones are electrically conductively connected to one another and the transistors are constructed or arranged in the substrate in such a manner that in each case free boundary faces of the two base zones lie opposite one another. The base connection is formed by an additionally doped zone in the interspace between the base zones, the doped zone having the same type of doping as the base zones.

Abstract: A charge coupled device circuit for use with a semiconductor Storage Unit or a semiconductor Logical Unit which includes at least a charge coupled device serially connected with a transistor between a supply voltage line and a reference potential (such as ground). The charge coupled device is located between the supply voltage line and the transistor. A further embodiment of the present invention includes, in addition to the above, a second transistor connected to form a flip-flop with the first transistor. A second charge coupled device is connected serially to the second transistor and in turn to the reference potential. The charge coupled device of this invention includes at least three control electrodes. A first electrode of each charge coupled device are connected to each other and to a first pulse line. A third electrode of each charge coupled device are connected to each other and to a second pulse line.

Abstract: Two semiconductor chips having complementary MOS circuits are interconnected by means of an output stage provided on the first chip and an input stage provided on the second chip. The connection is a high-speed connection despite the relatively high internal impedance of the MOS transistors. The output stage incorporates MOS transistors for transforming the signal level to a relatively low level, and the input stage incorporates MOS transistors interconnected as a pulsed trigger or amplifier for restoring the low signal to a relatively high level for connection to other MOS circuits.

Abstract: A static semiconductor storage element includes a flip-flop formed of a pair of complementary field effect transistors which are cross coupled without intersection to form a bistable circuit. One node of the flip-flop is connected to a terminal which is employed for both reading and writing functions. The flip-flop is set or reset by connection of an appropriate voltage to the node, and nondestructive read out is carried out by sensing the voltage level of the node.

Abstract: A storage arrangement employing first and second field effect transistors which are complementary to one another and connected in series, with the second transistor being of the depletion type, a load element, such as a resistor or transistor, being connected in series with such first mentioned transistors, with one side of such load element connected to the drain terminal of the first transistor and the other side of such load element connected to a line to which a supply voltage is connected, the drain-terminal of the second transistor being connected to a second line, which may form a word line, the gate terminal of the second transistor being connected to the drain terminal of the first transistor, and, preferably, a selector element such as a diode or transistor being operatively disposed between a third line and the junction of the load element and drain terminal of said first transistor, which third line may form a bit line, and a method of operating such arrangement.

Abstract: A complementary storage element with two inverters and one selector element is disclosed wherein an inverter in each case consists of a switching element and a load element connected in series with a junction point therebetween and wherein the selector element is connected to a digit line, and wherein the gate terminal of the selector element is operated by a word line, the two inverters being connected in series with their source terminals being connected together at a junction point and the terminals of the load elements which are not connected to the switching transistors each connected to a supply voltage line. The switching transistors are provided with feedback.

Abstract: A process for the production of a pair of complementary field effect transistors which have very short channel lengths. A lightly doped semiconductor layer is deposited on an electrically insulating substrate. A gate insulator layer is applied onto which first and second gate electrodes are formed for the two transistors. A masking oxide layer is applied to the exposed surface regions of the gate insulating layer and the gate electrodes. An opening is etched into the masking layer and gate insulator layer lying adjacent each gate electrode. Charge carriers of first and second types are diffused through the respective openings into the region of the semiconductor layer lying below to dope the same. This doping extends partially into the semiconductor region lying beneath a portion of the respective gate electrodes. All parts of the gate insulator layer except those parts lying beneath the gate electrodes are removed.