Abstract: In one embodiment, a method for processing a video signal includes: (1) receiving and storing luminance and chrominance information for each pixel in a first portion of the signal; (2) receiving luminance and chrominance information for each pixel in a second portion of the signal; (3) determining an estimated motion vector for each particular pixel of the second portion by comparing the luminance and chrominance information of the particular pixel to the stored luminance and chrominance information for one or more pixels in a search area of the first portion to determine a pixel in the search area that most closely matches the particular pixel and determining the estimated motion vector according to the particular pixel and the most closely matching pixel; (4) using the estimated motion vector to access the chrominance information for the most closely matching pixel; (5) using a three-dimensional comb filter to filter the chrominance information for the particular pixel and for the most closely matching pixe

Abstract: In one embodiment, a method for processing a video signal includes: (1) receiving and storing luminance and chrominance information for each pixel in a first portion of the signal; (2) receiving luminance and chrominance information for each pixel in a second portion of the signal; (3) determining an estimated motion vector for each particular pixel of the second portion by comparing the luminance and chrominance information of the particular pixel to the stored luminance and chrominance information for one or more pixels in a search area of the first portion to determine a pixel in the search area that most closely matches the particular pixel and determining the estimated motion vector according to the particular pixel and the most closely matching pixel; (4) using the estimated motion vector to access the chrominance information for the most closely matching pixel; (5) using a three-dimensional comb filter to filter the chrominance information for the particular pixel and for the most closely matching pixe

Abstract: A technique for detecting three modes of video input signal and outputting a vertical sync signal based on the input signal. In a first mode, a standard video signal is received and a line counter is used to decode and output the vertical sync. In a second mode where a non-standard signal is received, line counter cannot be used, but a vertical sync is detected and output. In a third mode, no video input signal is received, yet a vertical sync is output in free-running mode so that a blank screen is displayed.

Abstract: A video decoder circuit is provided with automatic AGC bias voltage calibration. The video decoder circuit has an input for receiving a video signal that is capacitively coupled to an analog front-end circuit. The decoder circuit includes a microprocessor-based control circuit coupled to the analog front-end circuit. The control circuit includes a bias circuit, a gain interface circuit for changing the amplitude of the video signal prior to filtering in a filter circuit, an offset circuit for changing the DC-level shift of the video signal, and a switching circuit for switching into a calibration mode by bypassing the filter circuit and connecting the gain interface circuit directly to an analog-to-digital conversion circuit of the analog front-end circuit.

Abstract: A digital filter for synthesized speech includes a full adder (72) that is multiplexed to perform multiplication and addition/subtraction operations. The inputs of the adder (72) are multiplexed by multiplexers (90) and (92). The adder (72) calculates Y-values and B-values. The B-values are input to a delay stack (116) and the Y-values are stored in a Y-register (78). One product is generated of a multiplier stored in a K-stack (128) and a multiplicand selected by a multiplexer (122). The multiplicand is a prestored summation that was earlier stored in a sum register (82). This product is stored in an ACC register (74) and utilized in both the calculation of the B-values and the Y-values. Therefore, only one multiplication is required for corresponding Y- and B-values, thereby reducing the number of multiplication steps required in processing each stage of a digital filter.

Abstract: A lattice filter for processing lattice equations includes a fast adder (78) for adding partial products to partially perform a multiplication step. A full adder (44) is provided for completing the multiplication and then adding the product with a previously calculated and stored value. The input to the full adder (44) is multiplexed with a multiplexer (74) for selecting the sum output of the fast adder (78) and a multiplexer (76) for selecting the carry output of the fast adder (78). The multiplexer (74) also selects prestored values for addition with the summed output of the full adder (44). This summed output is selected by the multiplexer (76). The fast adder (78) sums partial products simultaneous with addition operations of the full adder (44). In this manner, the full adder (44) operates at a slower rate than the fast adder (78). Storage registers (58), (62), (70) are utilized to delay results output by the full adder (44) for later selection and operation thereon.

Abstract: A system for processing a plurality of Equations includes a single full adder (44) which has the A input thereof multiplexed by multiplexer (62) and the B input thereof multiplexed by a multiplexer (94) and a multiplexer (66). The multiplexer (94) is operable to select a multiplicand for multiplication operations from a delay stack (54) for multiplication operations. The multiplication operation is performed by adding together partial products recording to Booth's modified algorithm. The partial products are generated by recode logic circuit (90) and (98). The recode logic circuits (90) and (98) are controlled by the multiplexed output from the multiplexer (80) which selects bits of a given multiplier stored in a K-stack (72). The multiplexer (62) in conjunction with the recode logic circuits (90) and (98) control reconfiguration of the adder (44) as a multiplication circuit.

Abstract: An LPC digital lattice filter includes a full adder (44) which has one input thereof multiplexed with a multiplexer (46) and the other input thereof multiplexed by a multiplexer (50). Combination of the multiplication and addition steps with the full adder (44) results in the calculation of one of the digital filter equations. The result of each of these equations is either a Y-value or a B-value. The Y-values are stored in the output of a Y-register (78) and the B-values are stored in a nine stage B-stack (100) for delay thereof. The multiplexer (60) selects multiplicands from either the output of the one stage delay (86), from the B-stack (100) or the input excitation I. The multiplexer (46) selects addends from either the output of the B-stack (100), the output of the B-register (96) or from the multiplexers (60) or (66). The values are calculated in an interleaved sequence with a Y-value calculated and then a B-value calculated utilizing this generated Y-value.

Abstract: A digital lattice filter includes a Y-adder (44) and a B-adder (106). The Y-adder (44) calculates the Y-values for a linear predictive coding voice compression technique and the B-adder (106) calculates the B-values. Each of the calculated B-values output by the B-adder (106) is input to a B-stack (118) for storage therein. The B-stack (118) delays the B-values for one sample period. Multiplier constants are contained in a K-stack (90) for output to both adders (44) and (106) for use in the multiplication operation. The final value is stored in a Y1-register (104). Each of the adders (44) and (106) are multiplexed to perform a multiplication operation followed by an addition operation to generate the respective Y- and B-values. A generated Y-value is stored in a Y-register (56) for use in the next sequential Y calculation. In addition, the generated Y-value is used as a multiplicand for generation of a B-value.

Abstract: A digital light-sensing control system for use in light sensitive equipment, such as a digital watch or a camera, is comprised of light sensor means such as a photo resistor, a digital brightness detector, and brightness control logic. The light sensor means produces analog signals which vary with ambient light intensity. The digital brightness detector selectively digitizes the analog signals to generate digital brightness signals. The brightness control logic generates system control signals in response to the digital brightness signals. Several embodiments of the digital brightness detector and the brightness control logic are disclosed. Each embodiment is capable of being integrated on a single semiconductor substrate.