Abstract: A method for manufacturing and operating a semiconductor device is disclosed. The semiconductor device includes a first capacitor node, a second capacitor node, a first capacitor electrode, a second capacitor electrode, a first switch and a second switch. The first switch is coupled between the first capacitor electrode and the first and second capacitor nodes such that the first switch has a first position that couples the first capacitor electrode to the first capacitor node and a second position that couples the first capacitor electrode to the second capacitor node. The second switch is coupled between the second capacitor electrode and the first and second capacitor nodes such that the second switch has a first position that couples the second capacitor electrode to the first capacitor node and a second position that couples the second capacitor electrode to the second capacitor node.

Abstract: A method for manufacturing and operating a semiconductor device is disclosed. The semiconductor device includes a first capacitor node, a second capacitor node, a first capacitor electrode, a second capacitor electrode, a first switch and a second switch. The first switch is coupled between the first capacitor electrode and the first and second capacitor nodes such that the first switch has a first position that couples the first capacitor electrode to the first capacitor node and a second position that couples the first capacitor electrode to the second capacitor node. The second switch is coupled between the second capacitor electrode and the first and second capacitor nodes such that the second switch has a first position that couples the second capacitor electrode to the first capacitor node and a second position that couples the second capacitor electrode to the second capacitor node.

Abstract: A method for manufacturing and operating a semiconductor device is disclosed. The semiconductor device includes a first capacitor node, a second capacitor node, a first capacitor electrode, a second capacitor electrode, a first switch and a second switch. The first switch is coupled between the first capacitor electrode and the first and second capacitor nodes such that the first switch has a first position that couples the first capacitor electrode to the first capacitor node and a second position that couples the first capacitor electrode to the second capacitor node. The second switch is coupled between the second capacitor electrode and the first and second capacitor nodes such that the second switch has a first position that couples the second capacitor electrode to the first capacitor node and a second position that couples the second capacitor electrode to the second capacitor node.

Abstract: One or more embodiments relate to a semiconductor chip including a capacitor arrangement, the capacitor arrangement comprising: a first capacitor; and a second capacitor stacked above the first capacitor, the first capacitor and the second capacitor coupled in series between a first metallization level and a second metallization level adjacent the first metallization level.

Abstract: One or more embodiments relate to a semiconductor chip including a capacitor arrangement, the capacitor arrangement comprising: a first capacitor; and a second capacitor stacked above the first capacitor, the first capacitor and the second capacitor coupled in series between a first metallization level and a second metallization level adjacent the first metallization level.

Abstract: A method for manufacturing and operating a semiconductor device is disclosed. The semiconductor device includes a first capacitor node, a second capacitor node, a first capacitor electrode, a second capacitor electrode, a first switch and a second switch. The first switch is coupled between the first capacitor electrode and the first and second capacitor nodes such that the first switch has a first position that couples the first capacitor electrode to the first capacitor node and a second position that couples the first capacitor electrode to the second capacitor node. The second switch is coupled between the second capacitor electrode and the first and second capacitor nodes such that the second switch has a first position that couples the second capacitor electrode to the first capacitor node and a second position that couples the second capacitor electrode to the second capacitor node.

Abstract: A semiconductor device includes a first capacitor node, a second capacitor node, a first capacitor electrode, a second capacitor electrode, a first switch and a second switch. The first switch is coupled between the first capacitor electrode and the first and second capacitor nodes such that the first switch has a first position that couples the first capacitor electrode to the first capacitor node and a second position that couples the first capacitor electrode to the second capacitor node. The second switch is coupled between the second capacitor electrode and the first and second capacitor nodes such that the second switch has a first position that couples the second capacitor electrode to the first capacitor node and a second position that couples the second capacitor electrode to the second capacitor node.

Abstract: A semiconductor device includes a first capacitor node, a second capacitor node, a first capacitor electrode, a second capacitor electrode, a first switch and a second switch. The first switch is coupled between the first capacitor electrode and the first and second capacitor nodes such that the first switch has a first position that couples the first capacitor electrode to the first capacitor node and a second position that couples the first capacitor electrode to the second capacitor node. The second switch is coupled between the second capacitor electrode and the first and second capacitor nodes such that the second switch has a first position that couples the second capacitor electrode to the first capacitor node and a second position that couples the second capacitor electrode to the second capacitor node.

Abstract: A two-step chemical mechanical polishing (CMP) process is provided for low dishing of metal lines in trenches in an insulation (oxide) layer, e.g., of silicon dioxide of a thickness of about 100-2000 nm, of a semiconductor wafer, e.g., of silicon, during its fabrication. The first step involves chemically mechanically polishing a metal layer, e.g., of copper of a thickness of about 200-2000 nm, disposed on the oxide layer and having a lower portion located in the trenches for forming metal lines and an upper portion overlying the lower portion. The first step polishing is effected at a high downforce, e.g., 3-8 psi, to remove at a high rate the upper portion of the metal layer substantially without removing the lower portion thereof and substantially without dishing of the lower portion located in the trenches. The second step involves continuing the CMP at a lower downforce, e.g.