Abstract: A system is disclosed that includes a fetch stage to retrieve an instruction to be utilized by processing units in a multi-path pipeline. The instruction can have selectors that can select functions to be performed by individual paths of the pipeline that can accept and utilize the same instruction. A first processing unit in a first path can execute a part of the retrieved instruction in response to the function selector, and a second processing unit can execute a part of the retrieved instruction in response to the function selector. Other embodiments are also disclosed.

Abstract: In some embodiments a system for processing video is disclosed. The system can include a video encoder/decoder module to accept video and to provide at least a portion of encoding functions on the video in a first mode and to perform at least a portion of decoding functions on video in a second mode. The system can also include an image processing module coupled to the video encoder/decoder, the image processing module having multiple modules to process images contained in the video. In addition the system can include a control unit coupled to the video encoder/decoder and the image processing module to determine an encoding mode of the encoder/decoder and to allocate resources of the image processing module to assist in encoding video. Other embodiments are disclosed.

Abstract: A digital processing device comprising a plurality of parallel processing units each coupled in parallel with one another. Each of the plurality of parallel processing units comprises at least one data memory storage unit; at least one input register coupled to the at least one data memory storage unit; and an arithmetic unit coupled to the at least one input register and configured to have synchronous command processing. A program execution control unit is coupled to each of the plurality of processing units and configured such that no processing clocks are required for synchronization of data transfer from the plurality of parallel processing units. At least one data bus is coupled to the at least one input register in each of the plurality of parallel processing units.

Abstract: In one embodiment, a method for operating a memory management system concurrently with a processing pipeline is disclosed. The method can include requesting data from a memory retrieval system utilizing a retrieval request, where the memory retrieval system can provide memory contents to a processing pipeline. In addition, an instruction can be processed by the processing pipeline, possibly a conditional instruction, that/which makes the retrieval request obsolete. The instruction can be associated with the identifier such that retrieve data from the memory can be associated with an instruction. The method can determine if the retrieval request is obsolete based on the results of processing of the instruction and the loading of the retrieved data into the pipeline can be forgone in response to determining that the retrieval request is obsolete.

Abstract: In one embodiment, a method for operating a memory management system concurrently with a processing pipeline is disclosed. The memory management system can fetch and effectively load registers to reduce stalling of the pipeline because the disclosed system provides improved data retrieval as compared to traditional systems. The method can include storing a memory request limit parameter, receiving a memory retrieval request from a multi-processor system to retrieve contents of a memory location and to place the contents in a predetermined location. The method can also include determining a number of pending memory retrieval requests, and then processing a new retrieval request if the number of pending memory retrieval requests is at or below the memory request limit parameter.

Abstract: In one embodiment a method for controlling instruction flow in a multiprocessor environment is disclosed. The method can include retrieving at least one slice instruction that is executable by more than one processing unit in a plurality of processing units. The method can also retrieve a global instruction that indicates a processing unit from a plurality of processing units that will receive the at least one slice instruction and the method can load the at least one slice instruction to the more than one processing unit in response to the global instruction. Such instruction control can allow the system to operate in a single input multiple data (SIMD) mode, a multiple instruction multiple data (MIMD) mode or a hybrid thereof.

Abstract: Methods and processor architectures for the execution of instruction having a condition are disclosed. Very long instruction words can be loaded from a memory unit into an instruction word decoder and the decoder can separate the VLIW into processable sequences. Each processable sequence can be processable by a processing unit among a plurality of processing units. Each processable sequence can be executed independently in the absence of a condition in the processable sequences, and when the processable sequences contain a condition, processing units can be logically coupled together to add processing resources to a processing intensive condition type code to assist in disposing of the conditional execution quickly by assigning these additional resources.