Patents by Inventor Karl-Heinz Kuesters
Karl-Heinz Kuesters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7662687Abstract: A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.Type: GrantFiled: April 28, 2008Date of Patent: February 16, 2010Assignee: Infineon Technologies AGInventors: Josef Willer, Thomas Mikolajick, Christoph Ludwig, Norbert Schulze, Karl Heinz Kuesters
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Publication number: 20090029512Abstract: A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.Type: ApplicationFiled: April 28, 2008Publication date: January 29, 2009Applicant: INFINEON TECHNOLOGIES AGInventors: Josef Willer, Thomas Mikolajick, Christoph Ludwig, Norbert Schulze, Karl Heinz Kuesters
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Patent number: 7368350Abstract: A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.Type: GrantFiled: December 20, 2005Date of Patent: May 6, 2008Assignee: Infineon Technologies AGInventors: Dominik Olligs, Torsten Mueller, Karl-Heinz Kuesters, Veronika Polei, Thomas Mikolajick, Josef Willer
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Patent number: 7365382Abstract: A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.Type: GrantFiled: February 28, 2005Date of Patent: April 29, 2008Assignee: Infineon Technologies AGInventors: Josef Willer, Thomas Mikolajick, Christoph Ludwig, Norbert Schulze, Karl-Heinz Kuesters
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Publication number: 20080081424Abstract: A layer of electrically conductive material is applied above a carrier surface. Gate electrodes are formed above a first area of the carrier surface from the electrically conductive material. An implantation of a dopant that is provided for source/drain regions is performed in the first area. The implant is annealed, and an auxiliary layer of a dielectric material is applied to planarize the surface. The first area is covered with a mask, and a further implantation of a dopant provided for source/drain regions is performed in a second area of the carrier surface provided for a memory cell array. The implant is annealed, and the memory cells are formed in the second area. The semiconductor memory device may comprise a selectively deposited electrically conductive material on the gate electrodes of the periphery and on buried bitlines of the memory cell array.Type: ApplicationFiled: September 29, 2006Publication date: April 3, 2008Inventors: Josef Willer, Karl-Heinz Kuesters
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Publication number: 20070231991Abstract: A semiconductor memory device includes a channel region, a gate electrode adjacent the channel region, and a charge-trapping layer between the channel region and the gate electrode. A voltage is applied between the gate electrode and the channel region to cause a first current of a first kind of charge carriers from the channel region to move into the charge-trapping layer and to cause a second current of a second kind of charge carriers from the gate electrode to move into the charge-trapping layer, until the value of the second current is at least half the amount of the first current value.Type: ApplicationFiled: March 31, 2006Publication date: October 4, 2007Inventors: Josef Willer, Nicolas Nagel, Thomas Mikolajick, Karl-Heinz Kuesters
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Patent number: 7250651Abstract: Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the semiconductor material by a tunnel dielectric having essentially the same tiny thickness throughout a primary tunnel area encompassing the area of curvature. The floating gate electrode may bridge the transistor body and is covered with a coupling dielectric provided for a control gate electrode, which forms part of a wordline.Type: GrantFiled: August 19, 2004Date of Patent: July 31, 2007Assignee: Infineon Technologies AGInventors: Karl-Heinz Küsters, Josef Willer, Corvin Liaw
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Publication number: 20070141799Abstract: A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.Type: ApplicationFiled: December 20, 2005Publication date: June 21, 2007Inventors: Dominik Olligs, Torsten Mueller, Karl-Heinz Kuesters, Veronika Polei, Thomas Mikolajick, Josef Willer
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Publication number: 20070082446Abstract: A method is provided for fabricating stacked non-volatile memory cells. A semiconductor wafer is provided having a plurality of diffusion regions forming buried bit lines. A charge-trapping layer and a conductive layer are deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed wherein an insulating layer is formed. An etch stop layer is deposited on the surface of the semiconductor wafer. Above the etch stop layer, a dielectric layer is deposited and is patterned so as to form contact holes. Subsequently, the contact holes are enlarged through the etch stop layer and the insulating layer to the buried bit lines.Type: ApplicationFiled: October 7, 2005Publication date: April 12, 2007Inventors: Dominik Olligs, Thomas Mikolajick, Josef Willer, Karl-Heinz Kuesters, Torsten Mueller
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Publication number: 20070042553Abstract: A storage layer sequence (20) and gate electrodes (34) are arranged on a substrate (10). The gate electrodes (34) may be fabricated in a gate electrode layer (22) made of electrically conductively doped polysilicon. Apart from an optional barrier layer (45), the word lines are solely formed from a material having a low resistivity, preferably from a metal layer (46). Word line spacers (52) are arranged on sidewalls for the purpose of electrical insulation and as a barrier against outdiffusion of metal atoms.Type: ApplicationFiled: August 17, 2006Publication date: February 22, 2007Inventors: Karl-Heinz Kuesters, Stephan Riedel, Josef Willer
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Publication number: 20060192266Abstract: A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.Type: ApplicationFiled: February 28, 2005Publication date: August 31, 2006Inventors: Josef Willer, Thomas Mikolajick, Christoph Ludwig, Norbert Schulze, Karl-Heinz Kuesters
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Patent number: 6590249Abstract: In a method for fabricating a dynamic memory cell in a semiconductor substrate having a trench capacitor 1 and a selection transistor 2 and a semiconductor memory having such a memory cell, a dielectric insulator layer 17, 201 is formed between the selection transistor and the trench capacitor, a first electrode region 203 of the selection transistor essentially being arranged above a block-type inner electrode 102 of the trench capacitor and being connected to said electrode via a contact opening 213 in the dielectric insulator layer, said contact opening being provided with an electrically conductive filling layer 214.Type: GrantFiled: June 11, 2002Date of Patent: July 8, 2003Assignee: Infineon Technologies AGInventors: Karl Heinz Küsters, Dietmar Temmler
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Patent number: 5025295Abstract: A three-dimensional, one transistor cell arrangement for dynamic semiconductor memories utilizing a trench capacitor in the substrate, and provided with a switching field effect transistor including an insulated gate electrode connected to the source/drain zone, the bit line contact for the connection of the switching transistor being arranged to be self-adjusted on the drain region in the semiconductor substrate, and overlapping the gate electrode with insulating layers on all sides. It also overlaps the neighboring field oxide region. The insulation layer laying beneath the bit line and over the gate level is a triple layer composed of silicon oxide/silicon nitride/silicon oxide, and in the through hole etching which is carried out by specific etching steps, there exists a self-adjusted overlapping contact. By eliminating the imprecision caused by the lithography, the space requirement of a memory cell can be reduced by about 20%. The invention is particularly utilized in the manufacture of 4 megabit DRAMs.Type: GrantFiled: January 16, 1990Date of Patent: June 18, 1991Assignee: Siemens AktiengesellschaftInventors: Karl-Heinz Kuesters, Wolfgang Mueller, Gerd Enders
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Patent number: 4962577Abstract: In a roll having a hollow roll through which a stationary cross piece extends, a bearing housing is provided for a bearing which engages an axial extension of the hollow roll. The extension has a smaller outer diameter than the outer diameter of the hollow roll. The bearing is located in the bearing housing between the outside circumference of the extension and the inside circumference of the bearing housing. The bearing housing has lubricant feed and discharge passages separate from means for hydraulically supporting the hollow roll. The bearing housing has a bore which fits over the end of the cross piece without play thereby forming a support distance.Type: GrantFiled: March 14, 1990Date of Patent: October 16, 1990Assignee: Eduard Kusters Maschinenfabrik GmbH & Co. KGInventors: Klaus Kubik, Karl-Heinz Kuesters
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Patent number: 4855801Abstract: A transistor varactor for dynamic semiconductor storage means which are formed on a doped silicon substrate having a high integration density and which includes one field effect transistor which has source and drain and a gate and a varactor overlaps the gate electrode and is formed as a stacked capacitor. The gate electrode and the varactor are electrically isolated from each other by insulating layers and the contact of the source zone is electrically isolated from the gate electrode by the insulating layers and the upper polysilicon layer of the varactor formed by oxidation of the side portions of the polysilicon layer. The contact of the source zone adjusts to the gate electrode and to the polysilicon layer in that the distance of the contact of the source zone relative to the gate electrode and the polysilicon layer is independent of the photographic accuracy. A buried contact between the polysilicon layer and the drain zone is self-adjusted relative to the gate electrode.Type: GrantFiled: July 16, 1987Date of Patent: August 8, 1989Assignee: Siemens AktiengesellschaftInventor: Karl-Heinz Kuesters