Abstract: Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.

Abstract: Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.

Abstract: Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.

Abstract: Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.

Abstract: Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.

Abstract: The interface between a memory device and a device requesting data from the memory device ensures that the data requested are read from the memory device and forwarded to the device requesting the data. The interface described is distinguished by the fact that if, following the reading of data from the memory device, there are no further requests from the device requesting data, it modifies the address previously used to read data from the memory device and arranges for the data stored at the address in the memory device to be read, and/or in that, at a predefined time following the initiation of the read operation, it accepts the data output by the memory device and/or starts the next memory access.

Abstract: Embodiments related to a processing unit and a first information storage are described and depicted.

Abstract: Embodiments related to a processing unit and a first information storage are described and depicted. First information is provided from a first unit into a first information storage for performing a first operation of the processing unit. During the first operation of the processing unit second information is transferred between the processing unit and the first information storage. The first information storage comprises during the first operation of the processing unit an access protection for the first unit.

Abstract: Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.

Abstract: Embodiments related to a processing unit and a first information storage are described and depicted.

Abstract: A method for operating a bus system, in particular in a microprocessor or microcontroller, and a semiconductor device for performing the method is disclosed. In one embodiment, for optimizing the order of accesses to the bus system, a method for operating a bus system includes at least one transmission channel, wherein the transmission channel connects at least two masters and at least one slave with one another. The masters are connected with an arbiter determining the order of accesses in which the masters access the transmission channel. The method provides that the arbiter takes into account meta information about planned accesses when determining the order of accesses. Meta information can further be stored and be referred to for subsequent determinations.

Abstract: A device that is connected to a bus can transmit data to one or more other devices and/or can receive data from other devices, through the bus, includes storage (i.e., memories or memory areas) in which data to be transmitted or received is temporarily stored, and a control device that determines whether or not any data is to be transmitted and, if appropriate, in which storage the data that are to be transmitted next is stored and/or in which storage the received data is to be stored. Information not contained in the data transmitted through the bus is stored in each storage, and is used to allocate a priority level to the respective storage, and the control device takes this information into account to decide the storage in which the next data to be transmitted will be stored and/or the storage in which the received data is to be stored.

Abstract: A method for operating a bus system, in particular in a microprocessor or microcontroller, and a semiconductor device for performing the method is disclosed. In one embodiment, for optimizing the order of accesses to the bus system, a method for operating a bus system includes at least one transmission channel, wherein the transmission channel connects at least two masters and at least one slave with one another. The masters are connected with an arbiter determining the order of accesses in which the masters access the transmission channel. The method provides that the arbiter takes into account meta information about planned accesses when determining the order of accesses. Meta information can further be stored and be referred to for subsequent determinations.

Abstract: A bus system has a bus, a number of units which can be connected to one another via the bus, and a bus controller. The units request the bus controller for bus access when they require a connection to one or more other units, and the bus controller decides which unit will be allocated to the bus. The bus system is distinguished in that at least some of the units which can request bus access are allocated values which indicate how long and/or how frequently the relevant unit can be allocated the bus or has been allocated the bus, and in that these values are used to decide whether a unit which is requesting bus access is allocated the bus, or whether a unit which requires bus access is requesting the bus at all.

Abstract: A device that is connected to a bus can transmit data to one or more other devices and/or can receive data from other devices, through the bus, includes storage (i.e., memories or memory areas) in which data to be transmitted or received is temporarily stored, and a control device that determines whether or not any data is to be transmitted and, if appropriate, in which storage the data that are to be transmitted next is stored and/or in which storage the received data is to be stored. Information not contained in the data transmitted through the bus is stored in each storage, and is used to allocate a priority level to the respective storage, and the control device takes this information into account to decide the storage in which the next data to be transmitted will be stored and/or the storage in which the received data is to be stored.

Abstract: A bus system has a bus, a number of units which can be connected to one another via the bus, and a bus controller. The units request the bus controller for bus access when they require a connection to one or more other units, and the bus controller decides which unit will be allocated to the bus. The bus system is distinguished in that at least some of the units which can request bus access are allocated values which indicate how long and/or how frequently the relevant unit can be allocated the bus or has been allocated the bus, and in that these values are used to decide whether a unit which is requesting bus access is allocated the bus, or whether a unit which requires bus access is requesting the bus at all.

Abstract: A program-controlled unit is described and is distinguished in that it has a connection which can be used to signal to it whether it is connected to a particular other circuit, and/or in that the program-controlled unit has a connection which it can use to signal to an external device that it is currently communicating or cooperating with a particular other device. Such a program-controlled unit can communicate and cooperate with devices connected to it better than has been the case to date, but at the same time can operate correctly under all circumstances even without these devices.

Abstract: The interface between a memory device and a device requesting data from the memory device ensures that the data requested are read from the memory device and forwarded to the device requesting the data. The interface described is distinguished by the fact that if, following the reading of data from the memory device, there are no further requests from the device requesting data, it modifies the address previously used to read data from the memory device and arranges for the data stored at the address in the memory device to be read, and/or in that, at a predefined time following the initiation of the read operation, it accepts the data output by the memory device and/or starts the next memory access.

Abstract: A description is given of a program-controlled unit, having a CPU and a memory management device. The memory management device, which, at the instigation of the CPU, writes data output by the CPU to a memory device, or reads out data stored in the memory device and forwards them to the CPU. The program-controlled unit described is distinguished by the fact that a control device is provided, which prescribes at least in part the instants at which the memory management device has to perform the actions required for carrying out a data transfer. What can thus be achieved is that, in phases in which the program-controlled unit uses a different memory device instead of a normally used memory device, the program-controlled unit behaves in precisely the same way as would be the case if the program-controlled unit currently used the normally used memory device.