Patents by Inventor Karl Hobart
Karl Hobart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110297958Abstract: A gate after diamond transistor and method of making comprising the steps of depositing a first dielectric layer on a semiconductor substrate, depositing a diamond particle nucleation layer on the first dielectric layer, growing a diamond thin film layer on the first dielectric layer, defining an opening for the gate in the diamond thin film layer, patterning of the diamond thin film layer for a gate metal to first dielectric layer surface, etching the first dielectric layer, depositing and defining a gate metal, and forming a contact window opening in the diamond thin film layer and the first dielectric layer to the ohmic contact.Type: ApplicationFiled: August 15, 2011Publication date: December 8, 2011Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Francis Kub, Karl Hobart
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Patent number: 8039301Abstract: A gate after diamond transistor and method of making comprising the steps of depositing a first dielectric layer on a semiconductor substrate, depositing a diamond particle nucleation layer on the first dielectric layer, growing a diamond thin film layer on the first dielectric layer, defining an opening for the gate in the diamond thin film layer, patterning of the diamond thin film layer for a gate metal to first dielectric layer surface, etching the first dielectric layer, depositing and defining a gate metal, and forming a contact window opening in the diamond thin film layer and the first dielectric layer to the ohmic contact.Type: GrantFiled: December 5, 2008Date of Patent: October 18, 2011Assignee: The United States of America as represented by the Secretary of the NavyInventors: Francis Kub, Karl Hobart
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Publication number: 20090146186Abstract: A gate after diamond transistor and method of making comprising the steps of depositing a first dielectric layer on a semiconductor substrate, depositing a diamond particle nucleation layer on the first dielectric layer, growing a diamond thin film layer on the first dielectric layer, defining an opening for the gate in the diamond thin film layer, patterning of the diamond thin film layer for a gate metal to first dielectric layer surface, etching the first dielectric layer, depositing and defining a gate metal, and forming a contact window opening in the diamond thin film layer and the first dielectric layer to the ohmic contact.Type: ApplicationFiled: December 5, 2008Publication date: June 11, 2009Applicant: The Government of the United State of America, as represented by the Secretary of the NavyInventors: Francis Kub, Karl Hobart
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Patent number: 7358152Abstract: A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer from the back surface; bonding the back surface of the wafer to a substrate using a thin bonding technique; and removing the support from the front surface of the wafer. A circuit comprising: a substrate; and a wafer; wherein the wafer is at most about 50 microns thick; wherein the wafer has a front surface comprising features; and wherein the wafer has a back surface bonded to the substrate using a thin bonding technique.Type: GrantFiled: November 22, 2005Date of Patent: April 15, 2008Assignee: The United States of America as represented by the Secretary of the NavyInventors: Francis Kub, Karl Hobart
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Patent number: 7303969Abstract: Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not necessarily in contact with, one of the injectors, and (iii) with a first quantum well adjacent to, but not necessarily in contact with, the bottom injector and a second quantum well adjacent to, but not necessarily in contact with, the top injector. Process parameters include temperature process for growth, deposition or conversion of the tunnel diode and subsequent thermal cycling which to improve device benchmarks such as peak current density and the peak-to-valley current ratio.Type: GrantFiled: August 21, 2001Date of Patent: December 4, 2007Assignee: The Ohio State UniversityInventors: Paul R. Berger, Phillip E. Thompson, Roger Lake, Karl Hobart, Sean L. Rommel
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Publication number: 20070018179Abstract: The Invention Is A Method For Making Power Device On A Semiconductor Wafer, Where The Backside Of The Wafer Has Been Thinned In Selected Regions To A Thickness Of About 25 Um By Reactive Ion Etching.Type: ApplicationFiled: September 22, 2006Publication date: January 25, 2007Inventors: Francis Kub, Karl Hobart
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Publication number: 20060199353Abstract: A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer from the back surface; bonding the back surface of the wafer to a substrate using a thin bonding technique; and removing the support from the front surface of the wafer. A circuit comprising: a substrate; and a wafer; wherein the wafer is at most about 50 microns thick; wherein the wafer has a front surface comprising features; and wherein the wafer has a back surface bonded to the substrate using a thin bonding technique.Type: ApplicationFiled: November 22, 2005Publication date: September 7, 2006Applicant: The Government of the USA, as represented by the Secretary of the Navy Naval Research LaboratoryInventors: Francis Kub, Karl Hobart
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Publication number: 20060118728Abstract: An apparatus and method for operating a direct wafer bonded semiconductor radiation detector includes bonding a plurality of wafers, receiving a radiation signal from a radiation source thereby producing electron and hole pairs via the radiation signal interacting with the detecting device. A voltage source produces a voltage across the direct bonded wafers, thereby drifting the electrons and holes through the plurality of bonded layers. The drifted electrons and/or holes include total drifted charge information of the detector and are collected and processed either at the detector or remote from the detector.Type: ApplicationFiled: October 25, 2005Publication date: June 8, 2006Inventors: Bernard Phlips, Francis Kub, Karl Hobart, James Kurfess
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Patent number: 6803598Abstract: Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not necessarily in contact with, one of the injectors, and (iii) with a first quantum well adjacent to, but not necessarily in contact with, the bottom injector and a second quantum well adjacent to, but not necessarily in contact with, the top injector. Process parameters include temperature process for growth, deposition or conversion of the tunnel diode and subsequent thermal cycling which to improve device benchmarks such as peak current density and the peak-to-valley current ratio.Type: GrantFiled: May 5, 2000Date of Patent: October 12, 2004Assignee: University of DelawareInventors: Paul R. Berger, Phillip E. Thompson, Roger Lake, Karl Hobart, Sean L. Rommel
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Patent number: 6562127Abstract: A method for making an array of thin single-crystal substrates on a handle substrate comprising the steps: attaching a plurality of single-crystal substrates to a face of a support wafer; polishing said plurality of attached single-crystal substrates so that said single-crystal substrates surfaces are coplanar on said support surface and to a selected surface roughness; implanting a hydrogen to a selected depth into said attached single-crystal substrates; bonding said polished and hydrogen implanted attached single-crystal substrates to a first handle substrate; and splitting said polished and hydrogen implanted attached single-crystal substrates at said selected depth thereby forming an array of thin single-crystal substrates on said first handle substrate and a support wafer having a remaining portion of said attached single-crystal substrates.Type: GrantFiled: January 16, 2002Date of Patent: May 13, 2003Assignee: The United States of America as represented by the Secretary of the NavyInventors: Francis Kud, Karl Hobart, Mike Spencer
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Publication number: 20030049894Abstract: Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not necessarily in contact with, one of the injectors, and (iii) with a first quantum well adjacent to, but not necessarily in contact with, the bottom injector and a second quantum well adjacent to, but not necessarily in contact with, the top injector. Process parameters include temperature process for growth, deposition or conversion of the tunnel diode and subsequent thermal cycling which to improve device benchmarks such as peak current density and the peak-to-valley current ratio.Type: ApplicationFiled: August 21, 2001Publication date: March 13, 2003Applicant: University of DelawareInventors: Paul R. Berger, Phillip E. Thompson, Roger Lake, Karl Hobart, Sean L. Rommel
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Patent number: 6274892Abstract: One embodiment of a semiconductor device includes a laterally extending semiconductor base, a buffer adjacent the base and having a first conductivity type dopant, and a laterally extending emitter adjacent the buffer and opposite the base and having a second conductivity type dopant. The buffer is relatively thin and has a first conductivity type dopant concentration greater than a second conductivity type dopant concentration in adjacent emitter portions to provide a negative temperature coefficient for current gain and a positive temperature coefficient for forward voltage for the device. The buffer may be silicon or germanium. A low temperature bonded interface may be between the emitter and the buffer or the buffer and the base. Another embodiment of a device may include a laterally extending localized lifetime killing portion between oppositely doped first and second laterally extending portions.Type: GrantFiled: March 9, 1998Date of Patent: August 14, 2001Assignee: Intersil Americas Inc.Inventors: Francis J. Kub, Victor Temple, Karl Hobart, John Neilson
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Patent number: 6194290Abstract: A method for making at least one semiconductor power device with current conduction in a vertical direction from a plurality of semiconductor substrates includes processing at least one surface of each of two semiconductor substrates to form at least one of a metal layer and a doped region. The substrates are bonded together so that the at least one processed surface of each of the two semiconductor substrates define outer surfaces of the semiconductor device. The method further includes annealing the bonded together substrates at an anneal temperature so as to not adversely effect the processed surfaces. The method allows the making of a double sided semiconductor power device with a reduction in the number of sequential processing steps. The direct bonding approach allows current production recipes for fabricating single sided power devices to be used without requiring a separate process sequence.Type: GrantFiled: March 9, 1998Date of Patent: February 27, 2001Assignee: Intersil CorporationInventors: Francis J. Kub, Victor Temple, Karl Hobart, John Neilson
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Patent number: 6153495Abstract: A method for making a semiconductor device from a plurality of semiconductor substrates includes the steps of: processing at least one surface of at least one of the substrates; thinning at least one of the substrates; bonding the processed and thinned substrates together so that the at least one processed surface defines an outer surface of the semiconductor device; and annealing the bonded together substrates at a relatively low anneal temperature so as to not adversely effect the at least one processed surface. The step of thinning preferably comprises removing a surface portion of the least one substrate opposite the processed surface, to a thickness of less than about 200 .mu.m. A gettering layer may be formed for the at least one substrate prior to thinning. Accordingly, the step of thinning removes the gettering layer. An implanted region may be formed at a surface of the at least one substrate opposite the processed surface prior to bonding.Type: GrantFiled: March 9, 1998Date of Patent: November 28, 2000Assignee: Intersil CorporationInventors: Francis J. Kub, Victor Temple, Karl Hobart, John Neilson