Abstract: A PLL system (200) includes a clock sequence generator (190). Clock sequence generator (190) provides a clock that steps down from a fast frequency through several steps to a frequency of zero. This step-down non-linear digression of frequencies causes a counter (110) driving a tank circuit of a self-calibrating VCO to achieve lock at an extremely rapid rate. The PFD (150) generates an analog signal based on the phase and frequency relationship of the reference and feedback clock signals. The analog signal is compared against an upper and lower reference voltage in a threshold detect circuit (120) and the signals UP and DOWN are supplied to the counter (110). The counter (110) provides a count value that controls the resonant frequency generated by the tank circuit. The convergence speed of the PLL system (200) is accelerated by the effects of the step-down clock provided by the clock sequence generator (190).

Abstract: A phase locked loop (20) includes a standby control circuit (30) and recovers from standby with minimum lock time. A reference counter (21), a loop counter portion (22, 23) and a phase detector (24) are disabled in response to an activation of a standby signal. Both the reference counter (21) and the loop counter portion (22, 23) are enabled in response to a deactivation of the standby signal. A voltage controlled oscillator (VCO) (26) output signal is decoupled from an input of the loop counter portion (22, 23) in response to an activation of a loop counter output signal. The VCO output signal is next recoupled to the input of the loop counter portion (22, 23) in response to an activation of a reference counter output signal. Finally, the phase detector (24) is enabled. In one embodiment, the loop counter portion (22, 23) includes a prescaler (22) which does not have a separate reset input, and a separate loop counter (23).

Abstract: A logic circuit for receiving both CMOS- and CML-level input voltages in one embodiment performs a logical OR function. A reference bipolar transistor is coupled to a first power supply voltage terminal through a first resistor. A second bipolar transistor for receiving a CML-level input signal is coupled to the first power supply voltage terminal through a second resistor. Emitters of the bipolar transistors are connected together. A MOS transistor for receiving a CMOS-level input signal has a drain connected to a collector of the second bipolar transistor, and a voltage dropping portion seperate the source of the MOS transistor from the emitters of the reference transistor and the bipolar transistor. The input voltages control a constant current conducted from a current source connected to the source of the MOS transistor. The logic circuit base-to-emitter reverse bias caused by CMOS logic levels.

Abstract: A circuit which provides a threshold voltage to a single-ended operated diode load emitter coupled logic circuit includes a transistor having an emitter coupled to an output at which the threshold voltage is produced, a collector coupled to a positive supply conductor and a diode coupled between the positive supply conductor and the base of the transistor. A current source is coupled to the emitter of the transistor which sinks a current that is equal to the "tail" current of the logic circuit. The magnitude of the threshold voltage produced is equal to a value that lies midway between the logic output voltage swing developed across the diode loads of the logic circuit.