Abstract: A versatile floating point adder which performs high speed floating point addition or subtraction on operands supplied in a signed magnitude format includes separate exponent and mantissa data paths for processing the exponent fields and mantissa fields of the floating point binary numbers to be added or subtracted. The exponent data path computes the absolute difference between the exponents of the floating point numbers, passes the large exponent, and adjusts the large exponent by an amount needed to normalize the mantissa and to reflect an overflow in the mantissa addition/substration and mantissa rounding operations. The mantissa data path denormalizes one of the input mantissas, adds the two mantissas after the denormalization operation, post-normalizes the resulting mantissa, and rounds the mantissa to the correct precision.

Abstract: A barrel-shift data shifter structure is modified to segregate switches in a switching matrix included therein into those switches as participate in a simple shift as well as in a barrel shift and those switches used only in a barrel shift. The former set of switches is controlled by shift control signals alone, and the latter set of switches responds to shift control signals and to the presence or absence of a rotation enable signal. The number of switches required is substantially smaller than required in a barrel shifter followed in cascade by a simple data shifter. Preferably provision is made for sticky bit generation. The sticky bit is the LOGIC OR response to all bits shifted to less significance than output data.

Abstract: A multiply/accumulator chip architecture capable of operating at a 20 megahertz system clock rate is designed so as to accept floating point numbers in sign magnitude form, to compute a product of the fractional portions thereof and to convert the fractional result into two's complement form for accumulation with the results of a previous product. This architecture readily permits the computation of vector-type inner product operations in a high speed pipelined fashion. Additionally, leading zero's and leadings one's detection is carried out in a multiply parallel fashion so as to rapidly produce post normalization results from the additive portion of the system. The system is implementable on a single integrated circuit chip in which an array multiplier is present so as to minimize inter-chip delays. The architecture of the present invention provides a high speed floating point multiply and accumulate operation with a short pipeline latency.