Abstract: Systems, apparatuses, and techniques for pulse width modulation (PWM) are described. A described system includes a circuit that contains an inductor and a transistor that controls current through the inductor based on a PWM signal to produce an output; and a controller to provide the PWM signal, which includes PWM cycles that include on-durations and off-durations. The controller can receive a first signal indicating an input voltage that is applied to the inductor, receive a second signal indicating a current through the inductor, use an on-duration parameter value to control the on-duration, determine a maximum off-duration of the off-durations corresponding to the PWM cycles occurring within a first voltage cycle, the first voltage cycle being defined between two consecutive zero-crossing events as indicated by the first signal, and adjust the on-duration parameter value for a second, subsequent voltage cycle based on the maximum off-duration to regulate the output voltage.

Abstract: Systems, methods, circuits and computer-readable mediums for system internal latency measurements in realtime applications are disclosed. In some implementations, a trigger signal is selected from a plurality of trigger signals for interrupting a processor of an integrated circuit system. The trigger signal includes a pulse having width. The system detects a rising edge of the pulse and starts a counter. The system detects a falling edge of the pulse and stops the counter. The system then compares a count of the counter with first and second values stored in first and second registers, respectively. The first value represents a minimum pulse width and the second value represents a maximum pulse width. The count is stored in the first or second register based on a result of the comparing.

Abstract: Systems, apparatuses, and techniques for pulse width modulation (PWM) are described. A described system includes a circuit that contains an inductor and a transistor that controls current through the inductor based on a PWM signal to produce an output; and a controller to provide the PWM signal, which includes PWM cycles that include on-durations and off-durations. The controller can receive a first signal indicating an input voltage that is applied to the inductor, receive a second signal indicating a current through the inductor, use an on-duration parameter value to control the on-duration, determine a maximum off-duration of the off-durations corresponding to the PWM cycles occurring within a first voltage cycle, the first voltage cycle being defined between two consecutive zero-crossing events as indicated by the first signal, and adjust the on-duration parameter value for a second, subsequent voltage cycle based on the maximum off-duration to regulate the output voltage.

Abstract: Systems, methods, circuits and computer-readable mediums for system internal latency measurements in realtime applications are disclosed. In some implementations, a trigger signal is selected from a plurality of trigger signals for interrupting a processor of an integrated circuit system. The trigger signal includes a pulse having width. The system detects a rising edge of the pulse and starts a counter. The system detects a falling edge of the pulse and stops the counter. The system then compares a count of the counter with first and second values stored in first and second registers, respectively. The first value represents a minimum pulse width and the second value represents a maximum pulse width. The count is stored in the first or second register based on a result of the comparing.

Abstract: A PWM architecture of a microcontroller is disclosed that includes a fault module for regulating and detecting faults in current sensing or illuminating devices (e.g., LED strings). The fault module is part of a hardware regulation loop of LED voltage and LED current that allows the CPU to be placed in idle mode (“IDLE”) while an LED string is regulated in illumination. The microcontroller includes a PWM generator having a double channels PWM timer with a specific fault mode and an amplified comparator with a voltage reference. The architecture allows tuning of various parameters, including LED peak current, LED voltage supply, LED voltage regulation step and LED dimming value. In IDLE mode, the hardware regulation loop can regulate LED peak current and LED voltage supply without any CPU resource (microcontroller in IDLE mode). The fault module part of the hardware regulation loop can also detect and inform the CPU of: 1) an open LED; 2) a weak battery; and 3) an LED voltage that is under a target value.

Abstract: Systems, apparatuses, and techniques for pulse width modulation (PWM) are described. A described system includes a circuit that contains an inductor and a transistor that controls current through the inductor based on a PWM signal to produce an output; and a controller to provide the PWM signal, which includes PWM cycles that include on-durations and off-durations. The controller can receive a first signal indicating an input voltage that is applied to the inductor, receive a second signal indicating a current through the inductor, use an on-duration parameter value to control the on-duration, determine a maximum off-duration of the off-durations corresponding to the PWM cycles occurring within a first voltage cycle, the first voltage cycle being defined between two consecutive zero-crossing events as indicated by the first signal, and adjust the on-duration parameter value for a second, subsequent voltage cycle based on the maximum off-duration to regulate the output voltage.

Abstract: A fault mode of a PWM module embedded in a microcontroller is used to detect main supply zero crossings for regulating output voltage of a PFC converter operating in BCM, without using an external detecting element or a comparator, ADC or other specialized component internal to the microcontroller. In some implementations, the end of decrease current flow in the energy storage inductor of the converter is used to reinitialize a PWM timer or counter (counting-up or counting-down timer). The current goes to zero for a time period when the main supply voltage goes to zero, resulting in the PWM timer or counter not being reinitialized prior to the end of the current PWM cycle. The failure to reinitialize the timer or counter can be used to generate a signal indicative of a zero voltage crossing of the main supply voltage.

Abstract: Systems, apparatuses, and techniques for pulse width modulation (PWM) are described. A described system includes a circuit that contains an inductor and a transistor that controls current through the inductor based on a PWM signal to produce an output; and a controller to provide the PWM signal, which includes PWM cycles that include on-durations and off-durations. The controller can receive a first signal indicating an input voltage that is applied to the inductor, receive a second signal indicating a current through the inductor, use an on-duration parameter value to control the on-duration, determine a maximum off-duration of the off-durations corresponding to the PWM cycles occurring within a first voltage cycle, the first voltage cycle being defined between two consecutive zero-crossing events as indicated by the first signal, and adjust the on-duration parameter value for a second, subsequent voltage cycle based on the maximum off-duration to regulate the output voltage.

Abstract: A counter circuit includes two pairs of registers configured to swap contents based on a timer overflow or underflow condition. The counter circuit also includes a waveform generator that generates a composite pulse width modulated signal with a period and duty cycle specified by values stored in the registers. A demultiplexing circuit generates first and second signals from the composite signal.

Abstract: Systems, apparatuses, and techniques for pulse width modulation (PWM) are described. A described system includes a circuit that contains an inductor and a transistor that controls current through the inductor based on a PWM signal to produce an output; and a controller to provide the PWM signal, which includes PWM cycles that include on-durations and off-durations. The controller can receive a first signal indicating an input voltage that is applied to the inductor, receive a second signal indicating a current through the inductor, use an on-duration parameter value to control the on-duration, determine a maximum off-duration of the off-durations corresponding to the PWM cycles occurring within a first voltage cycle, the first voltage cycle being defined between two consecutive zero-crossing events as indicated by the first signal, and adjust the on-duration parameter value for a second, subsequent voltage cycle based on the maximum off-duration to regulate the output voltage.

Abstract: A fault mode of a PWM module embedded in a microcontroller is used to detect main supply zero crossings for regulating output voltage of a PFC converter operating in BCM, without using an external detecting element or a comparator, ADC or other specialized component internal to the microcontroller. In some implementations, the end of decrease current flow in the energy storage inductor of the converter is used to reinitialize a PWM timer or counter (counting-up or counting-down timer). The current goes to zero for a time period when the main supply voltage goes to zero, resulting in the PWM timer or counter not being reinitialized prior to the end of the current PWM cycle. The failure to reinitialize the timer or counter can be used to generate a signal indicative of a zero voltage crossing of the main supply voltage.

Abstract: A PWM architecture of a microcontroller is disclosed that includes a fault module for regulating and detecting faults in current sensing or illuminating devices (e.g., LED strings). The fault module is part of a hardware regulation loop of LED voltage and LED current that allows the CPU to be placed in idle mode (“IDLE”) while an LED string is regulated in illumination. The microcontroller includes a PWM generator having a double channels PWM timer with a specific fault mode and an amplified comparator with a voltage reference. The architecture allows tuning of various parameters, including LED peak current, LED voltage supply, LED voltage regulation step and LED dimming value. In IDLE mode, the hardware regulation loop can regulate LED peak current and LED voltage supply without any CPU resource (microcontroller in IDLE mode). The fault module part of the hardware regulation loop can also detect and inform the CPU of: 1) an open LED; 2) a weak battery; and 3) an LED voltage that is under a target value.