Abstract: A method and circuit for implementing field effect transistors (FETs) having a gate within a gate utilizing a replacement metal gate process (RMGP), and a design structure on which the subject circuit resides are provided. A field effect transistor utilizing a RMGP includes a sacrificial gate in a generally central metal gate region on a dielectric layer on a substrate, a source and drain formed in the substrate, a pair of dielectric spacers, a first metal gate and a second metal gate replacing the sacrificial gate inside the central metal gate region, and a second gate dielectric layer separating the first metal gate and the second metal gate. A respective electrical contact is formed on opposite sides of the central metal gate region for respectively electrically connecting the first metal gate and the second metal gate to a respective voltage.

Abstract: Implementing circuit tuning post design of an integrated circuit utilizing gate phases. Each phase includes a designation of one of a slow phase and a fast phase. During the circuit design phase, each device is given a phase designation based upon expected performance of the device in the circuit. If the device is expected to be in a critical path or has a minimum timing slack, the device is placed on the fast phase. If the device is not in a critical path or has excess timing slack the device is placed on the slow phase.