Abstract: Various embodiments of the invention allow for improving measurement accuracy of monitoring devices, for example, to accurately determine speed from motion data measured by an accelerometer. In certain embodiments, this is accomplished by applying a classification process that resembles a random forest classification to recorded sample data to detect similarities to features associated with data for a known speed type, classifying sample data into speed types, and finally averaging the speed types to obtain a high accuracy estimate value for a final speed.

Abstract: Described herein are systems and methods for low-power voltage sensor circuits and current sensor circuits using an optically coupled isolator. In various embodiments, opto-couplers replace bulky transformers that are used in common designs. In embodiments, an optically coupled isolator is used as a power gate to reduce power consumption. Further power savings may be obtained by selecting appropriate phototransistors and adjustable bias resistors to set the forward current of a photodiode as small as functionally possible to reduce battery discharge while providing sufficient gain for the optical transistor. In certain embodiments, the bias voltage point may be chosen to be at the turn-on voltage of the photodiode. In embodiments, power consumption of the voltage and current sensors may be adjusted by adjusting the frequency of a power-gating control signal, which may be controlled by a microcontroller.

Abstract: A touch detection apparatus is provided, in which a touch panel is implemented with four surrounding edges. Three of the edges are embedded with retro-reflection materials. Light sources and pinholes are deployed on both corners of the touch panel, allowing reflections from the three edges to be projected on light sensors through the pinhole. The images projected on the light sensors are analyzed to determine coordinates of one or more contact points on the touch panel.

Abstract: An integrated circuit memory includes multiple memory banks grouped into repair groups Group0, Group1. One memory has redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells may be substituted for defective columns by multiplexing circuitry. This multiplexing circuitry shifts the bit lines selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry thereby reducing the number of redundant columns which need be provided.

Abstract: A touch detection apparatus is provided, in which a touch panel is implemented with four surrounding edges. Three of the edges are embedded with retro-reflection materials. Light sources and pinholes are deployed on both corners of the touch panel, allowing reflections from the three edges to be projected on light sensors through the pinhole. The images projected on the light sensors are analyzed to determine coordinates of one or more contact points on the touch panel.

Abstract: An integrated circuit memory is described having multiple memory banks which are grouped into repair groups Group0, Group1. One of the memory banks is provided with redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells are also provided and these may be substituted for defective columns by multiplexing circuitry. This multiplexing circuitry shifts the bit lines which are selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry thereby reducing the number of redundant columns which need be provided.

Abstract: A method of converting a static random access memory cell to a read only memory cell and the cell thus converted is disclosed. The cell to be converted comprises a data retention portion powered by a higher and lower voltage supply line and four transistors arranged as two cross coupled inverters. It is converted to a read only memory cell by severing a connection between at least one of said transistors within a first of said two inverters and one of said voltage supply lines such that when powered said first inverter outputs a predetermined value.

Abstract: An integrated circuit memory is described having multiple memory banks which are grouped into repair groups Group0, Group1. One of the memory banks is provided with redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells are also provided and these may be substituted for defective columns by multiplexing circuitry. This multiplexing circuitry shifts the bit lines which are selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry thereby reducing the number of redundant columns which need be provided.

Abstract: A method of converting a static random access memory cell to a read only memory cell and the cell thus converted is disclosed. The cell to be converted comprises a data retention portion powered by a higher and lower voltage supply line and four transistors arranged as two cross coupled inverters. It is converted to a read only memory cell by severing a connection between at least one of said transistors within a first of said two inverters and one of said voltage supply lines such that when powered said first inverter outputs a predetermined value.

Abstract: A memory cell includes polysilicon gates 2 running in a first direction. A sequence of layers metal lines includes a layer of bit lines 4 running in a second direction substantially orthogonal to the first direction followed by data lines 6 running in that second direction and then word lines 8 running in the first direction. The data lines 6 are precharged to a value which is held whilst the bit lines 4 are being used to sense data values stored within a memory cell.

Abstract: An integrated circuit memory 2 is described having multiple memory banks 4, 6, 8, 10, 12, 14, 16, 18 which are grouped into repair groups Group0, Group1. One of the memory banks 4, 18 is provided with redundant rows 20, 22 which can be used to substitute for a defective row 30, 32, 34 found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells 60, 62 are also provided and these may be substituted for defective columns 66, 68 by multiplexing circuitry 56, 58. This multiplexing circuitry shifts the bit lines which are selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry 56, 58 thereby reducing the number of redundant columns which need be provided.

Abstract: An integrated circuit memory includes memory cells 2 is connected to a power supply Vdd via a power supply control circuit 4. The power supply control circuit includes a first gate 26 and a second gate 28. The first gate 26 is switched by a write assist circuit so as to be non-conductive when writing to the memory cell 2. The second gate 28 is conductive both when writing to the memory cell 2 and when not writing to the memory cell 2. Accordingly, when a write operation is made a relatively high resistance path is formed through the power supply control circuit 4 compared to when writing is not being performed. This increase in the resistance through the power supply control circuit 4 during write operations induces a dip in the virtual supply voltage provided at the supply output of the power supply control circuit 4 in a manner which assist writes to be made.

Abstract: A memory cell is provided having polysilicon gates 2 running in a first direction. A sequence of layers metal lines are provided including layer of bit lines 4 running in a second direction substantially orthogonal to the first direction followed data lines 6 running in that second direction and then word lines 8 running in the first direction. The data lines 6 are precharged to a value which is held whilst the bit lines 4 are being used to sense data values stored within a memory cell.

Abstract: A memory device is provided comprising a memory array consisting of a plurality of memory cells. These memory cells are accessed via a plurality of word lines and a plurality of bit lines. Multiplexer logic is provided which has the plurality of bit lines connected to its inputs, and is arranged to connect one of those inputs to its output dependent on a multiplexer control signal. Decoder logic is responsive to an address to produce the multiplexer control signal and to select one of the word lines, as a result of which a particular memory cell in the memory array identified by the address has its associated bit line connected to the output of a multiplexer logic. Sense amp logic is coupled to the output of the multiplexer logic and has a precharge node used during a sensing operation to detect a stored data state of the particular memory cell.