Abstract: A system-on-a-chip controller having a first processor and a second processor. The first processor provides control processing and image processing. The second processor provides image processing. The processors receive data from an external source through a data bus. Also, the controller can include a third controller to provide I/O functionality to an external device. The second processor processes the stored data in either a row or column configuration. A fixed-length instruction word can be decoded into two instructions, an operation instruction and an I/O instruction, and can be used to process the data. The I/O instruction can be disposed in an unused bit field of the operation instruction.

Abstract: A system-on-a-chip controller having a first processor and a second processor. The first processor provides control processing and image processing. The second processor provides image processing. The processors receive data from an external source through a data bus. Also, the controller can include a third controller to provide I/O functionality to an external device. The second processor processes the stored data in either a row or column configuration. A fixed-length instruction word can be decoded into two instructions, an operation instruction and an I/O instruction, and can be used to process the data. The I/O instruction can be disposed in an unused bit field of the operation instruction.

Abstract: Embodiments of the present invention described herein relate to a method of fax and image data transmission, wherein the data are compressed using adaptive arithmetic compression algorithms. To achieve a simultaneous, secure encryption while compressing the data both a transmitter and a receiver use a same initialization of compression parameters and tables, which differs from a standard initialization and which is defined or referenced by encryption parameters. The encryption parameters are separately transmitted from the sender to the receiver for security and are used by the receiver to properly decode the encrypted data.

Abstract: Embodiments of the present invention are directed to a microcontroller system incorporating a DMA system and to a method of accessing a memory by a plurality of processing units. In embodiments of the present invention, the microcontroller system includes a plurality of processing units, a DMA module, and an interface to an external memory system. The DMA module controls access to the external memory system by the processing units on a time shared basis by allocating time slots to each of the plurality of processing units. The processing units can access the external memory system during their assigned time slots. Data transfers to and from the memory are accomplished in packets having a fixed maximum size.