Abstract: A hybrid window frame assembly includes a primary window frame formed of a first material connected to a cladding frame formed of a second material. The cladding frame includes a peripheral channel defining a recess that receives a peripheral bead of the window frame to connect the cladding frame to the window frame. The hybrid window frame further includes injection block cutouts at each corner. Each injection block cutout exposes at least a portion of respective inner sidewalls of the channel and bead. The hybrid window frame assembly further includes injection blocks inserted in each injection block cutout. Each injection block includes at least one injection hole accessible from an exterior of the hybrid window frame assembly. The hybrid window frame assembly further includes sealant injected through the at least one injection hole of each injection block to seal respective corners of the window frame and cladding frame together.

Abstract: A method, device and system for detecting error correction defects calculates a written error checking and correction (ECC) code for a written data and writes the written data and the written ECC code into a plurality of memory cells. When data is read from the memory cells including data representing ECC code, any errors are identified in the data from the ECC code. When the quantity of errors exceeds the correctable quantity supported by the ECC code, then the data is output “as-is” without attempts to correct the data or fail the memory device if the memory device is under test.

Abstract: A method, device and system for detecting error correction defects calculates a written error checking and correction (ECC) code for a written data and writes the written data and the written ECC code into a plurality of memory cells. When data is read from the memory cells including data representing ECC code, any errors are identified in the data from the ECC code. When the quantity of errors exceeds the correctable quantity supported by the ECC code, then the data is output “as-is” without attempts to correct the data or fail the memory device if the memory device is under test.

Abstract: Some embodiments of the invention include system and method for performing a calculation on the data associated with a group of wafers. The system and method display a wafer map having map indicators representing calculation results from the calculation. Other embodiments are described and claimed.