Abstract: In a D.C. coupled vertical deflection circuit, an input sawtooth signal is coupled to an inverting input of a vertical deflection amplifier via a first resistor network. A D.C. voltage is coupled to a second input of the amplifier via a second resistor network for preventing the D.C. signal component from affecting the deflection current. To provide temperature compensation, for every resistor included in the first resistor network, there is included a corresponding resistor of equal value in the second resistor network.

Abstract: A television receiver embodying the invention includes a plurality of luminance signal sources, each capacitively coupled to an input of a luminance signal selection switch and each capacitor being coupled to a respective clamp circuit with each clamp circuit having a reference voltage input coupled to a common reference voltage source. A sync separator is provided having a first input coupled to receive the output of luminance signal selection switch and a second input coupled to a source of reference potential derived from said reference voltage source. Advantageously, the overall number of clamp circuits is minimized by merging the sync separator circuit with the input signal selection clamping circuit.

Abstract: A signal slicer of a sync separator includes a comparator for generating an output signal in accordance with a difference between a black level restored video signal and a slice level. The slice level is established dynamically, in accordance with the peak level of the sync pulse between the peak of the sync pulse and the black level. When the sync pulse occurs in the video signal, the output signal of the signal slicer assumes an active, first logical state; conversely, between consecutively occurring sync pulses, the output signal assumes an inactive, second logical state. The slice level is clamped to a predetermined level to prevent the occurrence of the first logical state when no video signal is received.

Abstract: In a vertical sawtooth generator of a D.C. coupled vertical deflection circuit, a vertical deflection amplifier generates a sawtooth signal. Magnitudes of the sawtooth signal in first and second instants of its trace period are determined in accordance with first and second D.C. signals, respectively. The first and second D.C. signals are adjusted during service to control the raster height and the raster centering such that while the raster height is adjusted, raster centering is not significantly affected, and vice versa.

Abstract: A comparator circuit for an integrator comprises first and second transistors triggered by the integrator. The integrator has a current-controlled input. The transistors generate respective comparator output control signals which change when the transistors switch between saturated and unsaturated states. The first and second transistors are complementary transistors. A first current source, comprising a third transistor, is coupled to a source of supply voltage. One of the first and second transistors forms a corresponding mirrored current source with respect to the first current source. The integrator comprises an integration capacitor coupled to the mirrored current source. An output stage is responsive to the output control signals from the first and second transistors.

Abstract: A sawtooth signal generator of a D.C. coupled vertical deflection circuit is responsive, during service mode of operation, to a first signal at a D.C. level that is indicative of vertical centering. During the service mode operation, the generation of the sawtooth signal is disabled and, instead, the generator generates a D.C. signal that is D.C. coupled via a vertical deflection amplifier to a vertical deflection winding in a manner to position an electron beam at the vertical center of a display screen.

Abstract: The free-running frequency of a bus controlled horizontal oscillator is adjusted by programming of a first data signal that is coupled to a digital-to-analog converter. The programming causes the first data signal to be non-alterable. The programming is done during manufacturing of a wafer that includes the oscillator. A second data signal that is coupled from a microprocessor via a bus and via a second analog-to-digital converter to the oscillator can vary the oscillator free-running frequency to provide for tolerance compensation. The first data signal is immune against data errors. The second data signal is not immune against data errors, but can vary the oscillator frequency within only a relatively narrow range of values. Consequently, data errors are prevented from causing a significant change in the oscillator free-running frequency that might have occurred had both data signals been alterable.