Patents by Inventor Karl Sauter
Karl Sauter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9958496Abstract: A method and apparatus for determining misregistration of internal layers of a PCB using resistance measurements is disclosed. In one embodiment, a method includes measuring a first resistance between a first center terminal and a first peripheral terminal of a first registration coupon on a printed circuit board (PCB) panel including at least one PCB. The method further includes measuring a second resistance between the first center terminal and a second peripheral terminal of the first registration coupon, wherein the first and second peripheral terminals are associated with a first internal layer of the PCB. A difference between the first and second resistances is then calculated. Then, based on this difference, a determination is made of a distance of misregistration of the first internal layer, if any, along a first axis.Type: GrantFiled: August 28, 2015Date of Patent: May 1, 2018Assignee: Oracle International CorporationInventors: Stephanie Moran, Michael C. Freda, Karl Sauter
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Publication number: 20170059647Abstract: A method and apparatus for determining misregistration of internal layers of a PCB using resistance measurements is disclosed. In one embodiment, a method includes measuring a first resistance between a first center terminal and a first peripheral terminal of a first registration coupon on a printed circuit board (PCB) panel including at least one PCB. The method further includes measuring a second resistance between the first center terminal and a second peripheral terminal of the first registration coupon, wherein the first and second peripheral terminals are associated with a first internal layer of the PCB. A difference between the first and second resistances is then calculated. Then, based on this difference, a determination is made of a distance of misregistration of the first internal layer, if any, along a first axis.Type: ApplicationFiled: August 28, 2015Publication date: March 2, 2017Inventors: Stephanie Moran, Michael C. Freda, Karl Sauter
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Patent number: 9532233Abstract: A method for surveying a site for installation of wireless access points is provided. A map of the site under survey is displayed. User input relating to the position of a first wireless device at the site is received. User input relating to the position of a second wireless device at the site is also received. Wireless signals broadcast by the second wireless device are measured using the first wireless device to obtain signal strength values corresponding to the strength of the wireless signals. Attenuation values based on the signal strength values are calculated and assigned to features on the map of the site under survey.Type: GrantFiled: October 21, 2014Date of Patent: December 27, 2016Assignee: Xirrus, Inc.Inventors: Jack Michael Horner, Dirk Ion Gates, Kurt Karl Sauter, Bruce Anthony Miller, Alexander Chernyakhovsky
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Publication number: 20160245857Abstract: A step drill test structure for a PCB and method for using the same is disclosed. In one embodiment, a test structure includes a drill path and a connection via. The drill path may include sensing pads on selected ones of a plurality of layers of the PCB (e.g., the non-surface layers). The sensing pads of a given drill path may be electrically conductive, while the remaining portion of the drill path is non-conductive. The sensing pads of each drill path may be electrically coupled to the connection via. The depth of a given layer at a particular drill path may be determined by drilling, using an electrically conductive drill bit, into the drill path and determining when an electrical connection is made between the drill bit and the connection via.Type: ApplicationFiled: May 2, 2016Publication date: August 25, 2016Inventors: Stephanie Moran, Michael C. Freda, Karl Sauter
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Patent number: 9354270Abstract: A step drill test structure for a PCB and method for using the same is disclosed. In one embodiment, a test structure includes a drill path and a connection via. The drill path may include sensing pads on selected ones of a plurality of layers of the PCB (e.g., the non-surface layers). The sensing pads of a given drill path may be electrically conductive, while the remaining portion of the drill path is non-conductive. The sensing pads of each drill path may be electrically coupled to the connection via. The depth of a given layer at a particular drill path may be determined by drilling, using an electrically conductive drill bit, into the drill path and determining when an electrical connection is made between the drill bit and the connection via.Type: GrantFiled: June 13, 2014Date of Patent: May 31, 2016Assignee: Oracle International CorporationInventors: Stephanie Moran, Michael C Freda, Karl Sauter
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Publication number: 20150362547Abstract: A step drill test structure for a PCB and method for using the same is disclosed. In one embodiment, a test structure includes a drill path and a connection via. The drill path may include sensing pads on selected ones of a plurality of layers of the PCB (e.g., the non-surface layers). The sensing pads of a given drill path may be electrically conductive, while the remaining portion of the drill path is non-conductive. The sensing pads of each drill path may be electrically coupled to the connection via. The depth of a given layer at a particular drill path may be determined by drilling, using an electrically conductive drill bit, into the drill path and determining when an electrical connection is made between the drill bit and the connection via.Type: ApplicationFiled: June 13, 2014Publication date: December 17, 2015Inventors: Stephanie Moran, Michael C. Freda, Karl Sauter
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Publication number: 20150105087Abstract: A method for surveying a site for installation of wireless access points is provided. A map of the site under survey is displayed. User input relating to the position of a first wireless device at the site is received. User input relating to the position of a second wireless device at the site is also received. Wireless signals broadcast by the second wireless device are measured using the first wireless device to obtain signal strength values corresponding to the strength of the wireless signals. Attenuation values based on the signal strength values are calculated and assigned to features on the map of the site under survey.Type: ApplicationFiled: October 21, 2014Publication date: April 16, 2015Inventors: JACK MICHAEL HORNER, DIRK ION GATES, KURT KARL SAUTER, BRUCE ANTHONY MILLER, ALEXANDER CHERNYAKHOVSKY
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Patent number: 8868002Abstract: A method for surveying a site for installation of wireless access points is provided. A map of the site under survey is displayed. User input relating to the position of a first wireless device at the site is received. User input relating to the position of a second wireless device at the site is also received. Wireless signals broadcast by the second wireless device are measured using the first wireless device to obtain signal strength values corresponding to the strength of the wireless signals. Attenuation values based on the signal strength values are calculated and assigned to features on the map of the site under survey.Type: GrantFiled: August 31, 2011Date of Patent: October 21, 2014Assignee: Xirrus, Inc.Inventors: Jack Michael Horner, Dirk Ion Gates, Kurt Karl Sauter, Bruce Anthony Miller, Alexander Chernyakhovsky
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Publication number: 20130052961Abstract: A method for surveying a site for installation of wireless access points is provided. A map of the site under survey is displayed. User input relating to the position of a first wireless device at the site is received. User input relating to the position of a second wireless device at the site is also received. Wireless signals broadcast by the second wireless device are measured using the first wireless device to obtain signal strength values corresponding to the strength of the wireless signals. Attenuation values based on the signal strength values are calculated and assigned to features on the map of the site under survey.Type: ApplicationFiled: August 31, 2011Publication date: February 28, 2013Applicant: Xirrus, Inc.Inventors: Jack Michael Horner, Dirk Ion Gates, Kurt Karl Sauter, Bruce Anthony Miller, Alexander Chernyakhovsky
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Patent number: 7919804Abstract: An improved technique for power distribution for use by high speed integrated circuit devices. A mixture of high dielectric constant, Er and low Er materials are used in a dielectric layer sandwiched between the voltage and ground planes of a printed circuit board that is used to fixture one or more integrated circuit devices. The low Er material is used in an area contained by the location of the integrated circuit device and its corresponding decoupling capacitors located nearby. High Er material is used in areas between the regions of low Er material. The low Er material improves that speed at which current from an adjoining decoupling capacitor can propagate to a power pin of the integrated circuit device. The high Er material mitigates cross-coupling of noise between the low Er regions.Type: GrantFiled: December 1, 2006Date of Patent: April 5, 2011Assignee: Oracle America, Inc.Inventors: Kevin Horn, Forest Dillinger, Otto Richard Buhler, Karl Sauter
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Publication number: 20100236823Abstract: Systems and methods for providing plated through-holes (PTH) in PCBs, which advantageously allow improved soldering capabilities, are described herein. Such systems and methods are achieved by reducing the heat sinking effects of PTHs by providing one or more vias surrounding the PTHs to provide an electrical connection between the PTH and the internal and bottom conductive layers of a PCB. In this regard, the PTHs are spaced apart from at least one of the internal conductive layers (e.g., ground or power layers), so the heat sinking effects are reduced. This feature enables molten solder to substantially fill the entire PTH before freezing, thereby improving the mechanical and electrical connection between an electrical component and the PCB.Type: ApplicationFiled: March 18, 2009Publication date: September 23, 2010Applicant: SUN MICROSYSTEMS, INC.Inventors: LIEN-FEN HU, JORGE E. MARTINEZ-VARGAS, JR., SAMUEL M. LEE, KARL A. SAUTER, AARON MENDELSOHN
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Publication number: 20070102806Abstract: An improved technique for power distribution for use by high speed integrated circuit devices. A mixture of high dielectric constant, Er and low Er materials are used in a dielectric layer sandwiched between the voltage and ground planes of a printed circuit board that is used to fixture one or more integrated circuit devices. The low Er material is used in an area contained by the location of the integrated circuit device and its corresponding decoupling capacitors located nearby. High Er material is used in areas between the regions of low Er material. The low Er material improves that speed at which current from an adjoining decoupling capacitor can propagate to a power pin of the integrated circuit device. The high Er material mitigates cross-coupling of noise between the low Er regions.Type: ApplicationFiled: December 1, 2006Publication date: May 10, 2007Applicant: SUN MICROSYSTEMS, INC.Inventors: Kevin Horn, Forest Dillinger, Otto Buhler, Karl Sauter
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Patent number: 5710063Abstract: A method of locating a socket on a printed circuit board which includes the steps of fabricating a plurality of pads and one or more fiducials on the upper surface of the printed circuit board, optically aligning a drill with the fiducial, and then drilling a socket hole through the printed circuit board at the location defined by the fiducial. A peg of the socket is inserted into the socket hole to align the socket with the printed circuit board. Alternatively, a method for locating holes on a printed circuit board includes the steps of forming a master tooling hole through the printed circuit board, locating a fiducial on the printed circuit board using the master tooling hole as a guide, focusing on the fiducial with an optically alignable drill, thereby aligning the drill, and then drilling a hole through the printed circuit board using the aligned drill.Type: GrantFiled: June 6, 1996Date of Patent: January 20, 1998Assignee: Sun Microsystems, Inc.Inventors: Douglas W. Forehand, Karl A. Sauter