Abstract: Portions that identify motion are identified in an original frame of interlaced video fields. A de-interlaced version of the frame is generated. The original frame and the de-interlaced frame are combined to form a resulting frame, the resulting frame including portions from the original frame that represent relatively less motion and portions from the de-interlaced version that represent relatively more motion.

Abstract: A virtual processor mechanism and specific techniques and instructions for utilizing such virtual processor mechanism within an SIMD computer having numerous processors, and each physical processor having dedicated memory associated therewith. Each physical processor is used to simulate multiple "virtual" processors, with each physical processor simulating the same number of virtual processors. The memory of each physical processor is divided into n regions of equal size, each such region being allocated to one virtual processor, where n is the number of virtual processors simulated by each physical processor. Whenever an instruction is processed, each physical processor is time-sliced among the virtual memory regions, performing the operation first as one virtual processor, then another, until the operation has been performed for all virtual processors. Physical processors are switched among the virtual processors in a completely regular, predictable, deterministic fashion.

Abstract: A method is described for simulating additional processors in a SIMD computer by dividing the memory associated with each processor into a plurality of sub-memories and then operating on each sub-memory in succession as if it were associated with a separate processor. Thus, a first instruction or set of instructions is applied to all the processors of the array to cause at least some processors to process data stored at a first location or locations in the first sub-memory. Thereafter, the same first instruction or set of instructions is applied to all the processors of the array to cause at least some processors to process data stored at the same first location in a second sub-memory. And so forth for each of the sub-memories. By operating a SIMD computer in this fashion, it is possible in effect to vary the number of processors in the array so as to provide the number of processors required for a problem.

Abstract: A sensing device for generating an output signal corresponding to an input signal which comprises a substrate, an array of sensor elements for receiving the input signal and transfer members located on the surface of the substrate and interposed between the sensor elements. The sensor elements have their barycenters distributed on the surface of the substrate in a random non-periodic pattern. The transfer members are coupled to the sensor elements and generate the output signal.The sensing device is incorporated in an apparatus which generates an output signal from an input image wherein the output signal is substantially free of detectable aliases. The apparatus includes an image pick-up device for viewing the input image and transmitting radiation to the image sensing device, an analog-to-digital converter for converting the analog signal from a sensing device to a digital signal, a position encoder, an interpolator and a memory means for storing the output of the interpolator.