Abstract: The present disclosure provides a data processing system, method, and device. A method for monitoring a high definition map data collection trip includes recording data collected from one or more sensors associated with a vehicle, determining a current vehicle location, and determining whether the vehicle is following a planned route based on the current vehicle location. On a condition that the vehicle is not following the planned route, the method includes including an indication in the recorded data collected from the one or more sensors associated with the vehicle that the vehicle is off-route; generating additional navigation instructions, wherein the additional navigation instructions return the vehicle to the planned route; and providing the additional navigation instructions to a driver of the vehicle.

Abstract: The present disclosure provides a data processing system, method, and device for monitoring a high definition map data collection trip. A current vehicle location is determined. Whether the vehicle is following a planned route linked to a data collection trip, based on the current vehicle location is determined. On a condition that the vehicle is not following the planned route, a reason why the vehicle is not following the planned route is determined. An alert is generated, displayed on an in-vehicle navigation device, and uploaded with the reason to a command center.

Abstract: A component carrier and a method for manufacturing the same are disclosed. The component carrier includes an electrically conductive layer structure and an overhanging end. A first surface finish is formed on a first surface portion of the electrically conductive layer structure. Furthermore, the component carrier further includes a second surface finish on a second surface portion of the electrically conductive layer structure connected to the first surface finish and extending under the overhanging end.

Abstract: A component carrier being less prone to deterioration by oxidation and a method for manufacturing the same are disclosed. The component carrier includes a laminated stack with a first surface finish covering a first part of an exposed surface of the laminated stack and a second surface finish covering a second part of an exposed surface of the laminated stack. The first surface finish and the second surface finish are arranged in direct contact with one another so as to at least partially overlap.

Abstract: A component carrier and a method for manufacturing the same are disclosed. The component carrier includes an electrically conductive layer structure and an overhanging end. A first surface finish is formed on a first surface portion of the electrically conductive layer structure. Furthermore, the component carrier further includes a second surface finish on a second surface portion of the electrically conductive layer structure connected to the first surface finish and extending under the overhanging end.

Abstract: A component carrier being less prone to deterioration by oxidation and a method for manufacturing the same are disclosed. The component carrier includes a laminated stack with a first surface finish covering a first part of an exposed surface of the laminated stack and a second surface finish covering a second part of an exposed surface of the laminated stack. The first surface finish and the second surface finish are arranged in direct contact with one another so as to at least partially overlap.

Abstract: An integrated circuit memory includes memory cells 2 is connected to a power supply Vdd via a power supply control circuit 4. The power supply control circuit includes a first gate 26 and a second gate 28. The first gate 26 is switched by a write assist circuit so as to be non-conductive when writing to the memory cell 2. The second gate 28 is conductive both when writing to the memory cell 2 and when not writing to the memory cell 2. Accordingly, when a write operation is made a relatively high resistance path is formed through the power supply control circuit 4 compared to when writing is not being performed. This increase in the resistance through the power supply control circuit 4 during write operations induces a dip in the virtual supply voltage provided at the supply output of the power supply control circuit 4 in a manner which assist writes to be made.

Abstract: A content addressable memory system has a plurality of associated circuit sets (12). Each circuit set has a tag memory element, a latching circuit and a data memory element. Each tag memory element stores a received tag in a first mode of operation and compares a received data tag to a stored data tag in a second mode of operation. In the second mode of operation, the tag memory element couples a first voltage supply terminal to an associated node in response to the comparison. Each latching circuit latches the voltage level present on its associated node during a first phase of a control signal. Each data memory element stores a data word and outputs the data word responsive to the latched voltage level of the associated latching circuit. The latching circuit continues to latch the voltage level and the data memory element continues to output its data word for an entire clock cycle.

Abstract: A memory (20) has a read cycle and a write cycle. During the read cycle, differential data signals, corresponding to data provided by a selected memory cell, are superimposed on a first common mode voltage and provided to data output buffers (70-73). During the write cycle, differential data signals on read global data lines (61-62) are equalized at a second common mode voltage and data output buffers (70-73) are disabled. Output enable circuit (74) provides an output enable signal halfway between the first and second common mode voltages. Data output buffers (70-73) are enabled at the beginning of the read cycle when the differential data signals cross the output enable signal as they transition from the second common mode voltage to the first common mode voltage. Enabling data output buffers (70-73) in this way greatly relaxes output enable timing constraints.