Patents by Inventor Karl Zapf

Karl Zapf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8188780
    Abstract: A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means which hold a logic hold level to be tapped off as a stored logic state of the logic signal. The logic hold level is adjustable to a first logic level by a first push-pull transistor controlled by the set signal and to a second logic level by a second push-pull transistor controlled by the reset signal.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: May 29, 2012
    Assignee: Infineon Technologies AG
    Inventors: Christian Pacha, Siegmar Köppe, Karl Zapf
  • Patent number: 7898836
    Abstract: An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: March 1, 2011
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kuenemund, Karl Zapf, Artur Wroblewski
  • Publication number: 20090323389
    Abstract: An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.
    Type: Application
    Filed: April 21, 2008
    Publication date: December 31, 2009
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: THOMAS KUENEMUND, Karl Zapf, Artur Wroblewski
  • Publication number: 20070182473
    Abstract: A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means which hold a logic hold level to be tapped off as a stored logic state of the logic signal. The logic hold level is adjustable to a first logic level by a first push-pull transistor controlled by the set signal and to a second logic level by a second push-pull transistor controlled by the reset signal.
    Type: Application
    Filed: December 29, 2006
    Publication date: August 9, 2007
    Applicant: Infineon Technologies AG
    Inventors: Christian Pacha, Siegmar Koppe, Karl Zapf
  • Patent number: 4271461
    Abstract: A clock-controlled dc converter is provided in integrated semiconductor MOS technology and serves the supply voltage of integrated MOS circuits, particularly dynamic memories. The converter comprises a clock pulse generator having two outputs, supplying sequences of clock pulses which are inverted with respect to one another, which pulses are connected to the two clock pulse inputs of a first pulse level shifter. The first pulse level shifter comprises a bistable flip-flop lying at a supply potential, and which is switched as a level shifter. The two outputs of the first level shifter are connected, on the one hand, to the output of a voltage converter by way of the source-drain circuit of a respective field effect transistor. On the other hand, the two outputs are connected to the supply input of a respective pulse voltage doubler, which are in turn directly charged by a respective output of the clock pulse generator.
    Type: Grant
    Filed: May 4, 1979
    Date of Patent: June 2, 1981
    Assignee: Siemens Aktiengesellschaft
    Inventors: Kurt Hoffmann, Karl Zapf