Abstract: An I/O system including a processor, a multitasking operating system and DMA hardware efficiently controls a transfer of data between a main memory and memories of different types of devices by minimizing context switches between tasks and wait times of the tasks. A plurality of validation routines are used to validate a plurality of commands when the validation routines are called. Each of the commands corresponds to a specific type of I/O operation and a specific one of the device memories to participate in the I/O operation with the main memory. Each of the validation routines is device type specific and command type specific. A general routine responds to each of the commands by identifying and calling the validation routine which corresponds to the type of I/O operation and type of device which are specified in the command. The general routine initiates I/O hardware after the validation routine validates the command.

Abstract: A communications adapter interconnects a first device exhibiting a two way alternate (TWA) protocol and a second device exhibiting a two way simultaneous (TWS) protocol. The communications adapter comprises a transmit buffer for storing data received from the first device via a first communication link for transmission to the second device via a second communication link, and a receive buffer for storing data received from the second device via the second communication link for transmission to the first device via the first communication link. Data can be transferred in either direction between the transmit or receive buffer and the first device faster than in the same direction between the transmit or receive buffer and the second device.