Patents by Inventor Karol A. Szerszen
Karol A. Szerszen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240354886Abstract: An apparatus to facilitate compression of memory data is disclosed. The apparatus comprises one or more processors to receive uncompressed data, adapt a format of the uncompressed data to a compression format, perform a color transformation from a first color space to a second color space, perform a residual computation to generate residual data, compress the residual data via entropy encoding to generate compressed data and packing the compressed data.Type: ApplicationFiled: March 8, 2024Publication date: October 24, 2024Applicant: Intel CorporationInventors: Sreenivas Kothandaraman, Karthik Vaidyanathan, Abhishek R. Appu, Karol Szerszen, Prasoonkumar Surti
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Patent number: 12086120Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.Type: GrantFiled: December 15, 2022Date of Patent: September 10, 2024Assignee: INTEL CORPORATIONInventors: Prasoonkumar Surti, Abhishek R. Appu, Karol Szerszen, Eric Liskay, Karthik Vaidyanathan
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Patent number: 11983791Abstract: An apparatus to facilitate compression of memory data is disclosed. The apparatus comprises one or more processors to receive uncompressed data, adapt a format of the uncompressed data to a compression format, perform a color transformation from a first color space to a second color space, perform a residual computation to generate residual data, compress the residual data via entropy encoding to generate compressed data and packing the compressed data.Type: GrantFiled: September 14, 2020Date of Patent: May 14, 2024Assignee: Intel CorporationInventors: Sreenivas Kothandaraman, Karthik Vaidyanathan, Abhishek R. Appu, Karol Szerszen, Prasoonkumar Surti
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Publication number: 20240104825Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.Type: ApplicationFiled: October 3, 2023Publication date: March 28, 2024Inventors: Karol SZERSZEN, Prasoonkumar SURTI, Gabor LIKTOR, Karthik VAIDYANATHAN, Sven WOOP
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Patent number: 11783530Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.Type: GrantFiled: February 22, 2022Date of Patent: October 10, 2023Assignee: INTEL CORPORATIONInventors: Karol Szerszen, Prasoonkumar Surti, Gabor Liktor, Karthik Vaidyanathan, Sven Woop
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Publication number: 20230252010Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.Type: ApplicationFiled: December 15, 2022Publication date: August 10, 2023Applicant: Intel CorporationInventors: Prasoonkumar Surti, Abhishek R. Appu, Karol Szerszen, Eric Liskay, Karthik Vaidyanathan
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Publication number: 20230205704Abstract: A graphics processor includes multiple levels of memory units, including a memory device and a cache device located near a graphics component. The graphics processor includes distributed compression/decompression, including a module between the cache device and the memory device. The module can perform compression of write data when the write data is moved from the cache device to the memory device, and perform decompression of read data when the read data is moved from the memory device to the cache device. The graphics processor can include a second level of cache with another compression module between the first level of cache and the second level of cache.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Prasoonkumar SURTI, Vidhya KRISHNAN, Abhishek R. APPU, Karol A. SZERSZEN, Lakshminarayanan STRIRAMASSARMA
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Publication number: 20230206383Abstract: A system includes a compression engine that stores the compression format information embedded in the compressed data. The compression format information can be included in a header that includes compression control surface (CCS) information. The system includes a shared memory to store compressed data for multiple hardware pipelines, where blocks of the compressed data have a common memory footprint and the compression header. The compression engine can compress data to store in the shared memory including generation of the header. The compression engine can decompress data read from the shared memory, including identification of the compression format from the header.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Karol A. SZERSZEN, Prasoonkumar SURTI, Vidhya KRISHNAN, Aditya NAVALE, Abhishek R. APPU, Altug KOKER, Ronald W. SILVAS
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Publication number: 20230096188Abstract: Examples include techniques for a fast clear of a 3-dimensional (3D) surface. Examples include re-describing 3D surface to a 2D surface using various dimension of the 3D surface as inputs in an algorithm to output a 2-dimensional (2D) surface as a re-description of the 3D surface. The algorithm to also includes additional inputs associated with a tiling mode used to read or write the 3D surface to a graphics display and a bit per pixel format to output the 2D surface. 2D surface width and height associated with the outputted 2D surface is included in a clear command to cause the 3D surface to be cleared.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Karol A. SZERSZEN, Prasoonkumar SURTI, Abhishek R. APPU, John H. FEIT
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Publication number: 20230099093Abstract: A graphics processing apparatus includes graphics processors connected by a network connection, where the graphics processors pass compressed data. A first graphics processor stores data blocks as compressed data in a memory. The compressed data has data blocks of variable size, where a size of a block of compressed data depends on a compression ratio of the block of compressed data. A second graphics processor also stores data blocks as compressed data. The first graphics processor concatenates a variable number of blocks of compressed data into a packet of fixed size to send to the second graphics processor. The packet has a variable number of blocks of compressed data depending on the compression ratios of the multiple blocks of compressed data.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Karol A. SZERSZEN, Prasoonkumar SURTI, Abhishek R. APPU
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Patent number: 11615584Abstract: Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.Type: GrantFiled: July 22, 2021Date of Patent: March 28, 2023Assignee: Intel CorporationInventors: Vasanth Ranganathan, Saikat Mandal, Saurabh Sharma, Vamsee Vardhan Chivukula, Karol A. Szerszen, Aleksander Olek Neyman, Altug Koker, Prasoonkumar Surti, Abhishek Appu, Joydeep Ray, Art Hunter, Luis F. Cruz Camacho, Akshay R. Chada
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Publication number: 20230062540Abstract: Examples described herein relate to a manner of determining a number of bits to encode compression data. Some examples include: compressing pixel data of a region of pixels in a frame; determining a number of bits associated with at least two partitions; utilizing the determined number of bits to encode residual values generated from the compressing the pixel data; and storing the encoded residual values. In some examples, the at least two partitions comprise a first partition and a second partition. Some examples include: encoding residuals in the first partition using a number of bits associated with the first partition and encoding residuals in the second partition using a number of bits associated with the second partition.Type: ApplicationFiled: August 18, 2021Publication date: March 2, 2023Inventors: Prasoonkumar SURTI, Abhishek R. APPU, Karol A. SZERSZEN, Karthik VAIDYANATHAN, Sreenivas KOTHANDARAMAN, Mohamed FAROOK
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Patent number: 11574382Abstract: Examples described herein relate to a decompression engine that can request compressed data to be transferred over a memory bus. In some cases, the memory bus is a width that requires multiple data transfers to transfer the requested data. In a case that requested data is to be presented in-order to the decompression engine, a re-order buffer can be used to store entries of data. When a head-of-line entry is received, the entry can be provided to the decompression engine. When a last entry in a group of one or more entries is received, all entries in the group are presented in-order to the decompression engine. In some examples, a decompression engine can borrow memory resources allocated for use by another memory client to expand a size of re-order buffer available for use. For example, a memory client with excess capacity and a slowest growth rate can be chosen to borrow memory resources from.Type: GrantFiled: September 3, 2021Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Abhishek R. Appu, Eric G. Liskay, Prasoonkumar Surti, Sudhakar Kamma, Karthik Vaidyanathan, Rajasekhar Pantangi, Altug Koker, Abhishek Rhisheekesan, Shashank Lakshminarayana, Priyanka Ladda, Karol A. Szerszen
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Publication number: 20230030741Abstract: Compressed verbatim copy can enable more efficient copying of compressed data. In one example, a compressed verbatim copy method involves receiving a command to copy compressed data from a source address of the memory device to a destination address. In response to the receipt of the command, the method involves copying the compressed data in a compressed format from the source address to the destination address without first decompressing the data. A second source address and a second destination address of metadata for the compressed data is determined, and the metadata is copied from the second source address to the second destination address.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Inventors: Nilay MISTRY, Karol A. SZERSZEN, Prasoonkumar SURTI, Ronald W. SILVAS
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Patent number: 11556511Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.Type: GrantFiled: April 1, 2019Date of Patent: January 17, 2023Assignee: Intel CorporationInventors: Prasoonkumar Surti, Abhishek R. Appu, Karol Szerszen, Eric Liskay, Karthik Vaidyanathan
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Publication number: 20220414977Abstract: Methods, systems and apparatuses may provide for technology that identifies first graphics data that is associated with spatially proximate positions. The technology identifies second graphics data that is associated with spatially proximate positions, and interleaves the first and the second graphics data across a plurality of storage tiles.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Prasoonkumar Surti, Ronald Silvas, Karol A. Szerszen
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Publication number: 20220383444Abstract: Generation and storage of compressed z-planes in graphics processing is described. An example of a processor includes a rasterizer to generate a fragment of pixel data including blocks of pixel data; a depth pipeline to receive the fragment, the pipeline including a first and second depth test hardware, the first depth test hardware to perform a coarse depth test including determining minimum and maximum depths for each block; and a depth buffer, wherein the processor is to determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data and passes a first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Applicant: Intel CorporationInventors: Saikat Mandal, Karol Szerszen, Vasanth Ranganathan, Altug Koker, Michael Norris, Prasoonkumar Surti, Takahiro Murata
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Publication number: 20220262063Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.Type: ApplicationFiled: February 22, 2022Publication date: August 18, 2022Inventors: Karol SZERSZEN, Prasoonkumar SURTI, Gabor LIKTOR, Karthik VAIDYANATHAN, Sven WOOP
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Publication number: 20220084156Abstract: An apparatus to facilitate compression of memory data is disclosed. The apparatus comprises one or more processors to receive uncompressed data, adapt a format of the uncompressed data to a compression format, perform a color transformation from a first color space to a second color space, perform a residual computation to generate residual data, compress the residual data via entropy encoding to generate compressed data and packing the compressed data.Type: ApplicationFiled: September 14, 2020Publication date: March 17, 2022Applicant: Intel CorporationInventors: Sreenivas Kothandaraman, Karthik Vaidyanathan, Abhishek R. Appu, Karol Szerszen, Prasoonkumar Surti
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Patent number: 11263800Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.Type: GrantFiled: December 27, 2019Date of Patent: March 1, 2022Assignee: INTEL CORPORATIONInventors: Karol Szerszen, Prasoonkumar Surti, Gabor Liktor, Karthik Vaidyanathan, Sven Woop