Patents by Inventor Karol F. Menezes
Karol F. Menezes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8347066Abstract: Replay instruction morphing. One disclosed apparatus includes an execution unit to execute an instruction. A replay system replays an altered instruction if the execution unit executes the instruction erroneously.Type: GrantFiled: February 28, 2005Date of Patent: January 1, 2013Assignee: Intel CorporationInventors: Douglas M. Carmean, David J. Sager, Thomas F. Toll, Karol F. Menezes
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Patent number: 7366881Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.Type: GrantFiled: April 11, 2005Date of Patent: April 29, 2008Assignee: Intel CorporationInventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Patent number: 6925553Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, is received. The macro instruction is then split into a first micro instruction and a second micro instruction, the first micro instruction specifying the operation on a first corresponding segment including a first portion of the first data operand and a first portion of the second data operand, and the second micro instruction specifying the operation on a second corresponding segment including a second portion of the first data operand and a second portion of the second data operand. The first and second micro instructions are then executed.Type: GrantFiled: October 20, 2003Date of Patent: August 2, 2005Assignee: Intel CorporationInventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Patent number: 6880069Abstract: Replay instruction morphing. One disclosed apparatus includes an execution unit to execute an instruction. A replay system replays an altered instruction if the execution unit executes the instruction erroneously.Type: GrantFiled: June 30, 2000Date of Patent: April 12, 2005Assignee: Intel CorporationInventors: Douglas M. Carmean, David J. Sager, Thomas F. Toll, Karol F. Menezes
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Publication number: 20040083353Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, is received. The macro instruction is then split into a first micro instruction and a second micro instruction, the first micro instruction specifying the operation on a first corresponding segment including a first portion of the first data operand and a first portion of the second data operand, and the second micro instruction specifying the operation on a second corresponding segment including a second portion of the first data operand and a second portion of the second data operand. The first and second micro instructions are then executed.Type: ApplicationFiled: October 20, 2003Publication date: April 29, 2004Inventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Patent number: 6694426Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.Type: GrantFiled: June 6, 2002Date of Patent: February 17, 2004Assignee: Intel CorporationInventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Patent number: 6687810Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.Type: GrantFiled: June 6, 2002Date of Patent: February 3, 2004Assignee: Intel CorporationInventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Publication number: 20020184474Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.Type: ApplicationFiled: June 6, 2002Publication date: December 5, 2002Inventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Publication number: 20020178348Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.Type: ApplicationFiled: June 6, 2002Publication date: November 28, 2002Inventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Patent number: 6425073Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.Type: GrantFiled: March 13, 2001Date of Patent: July 23, 2002Assignee: Intel CorporationInventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes
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Publication number: 20010034826Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.Type: ApplicationFiled: March 13, 2001Publication date: October 25, 2001Inventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Bosewell, Karol F. Menezes
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Patent number: 6230257Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.Type: GrantFiled: March 31, 1998Date of Patent: May 8, 2001Assignee: Intel CorporationInventors: Patrice Roussel, Glenn J. Hinton, Shreekant S. Thakkar, Brent R. Boswell, Karol F. Menezes