Abstract: A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.

Abstract: An IC controller for a USB Type-C device includes a register that is programmable to store a pulse width and a frequency. A buck-boost converter of the controller includes a first high-side switch and a second high-side switch. Control logic is coupled to the register and gates of the first/second high-side switches. To perform a soft start in one of buck mode or boost mode, the control logic: causes the second high-side switch to operate in diode mode; retrieves values of the pulse width and the frequency from the register; causes the first high-side switch to turn on using pulses having the pulse width and at the frequency; detects an output voltage at the output terminal of the buck-boost converter that exceeds a threshold value; and in response to the detection, transfers control of the buck-boost converter to an error amplifier loop coupled to the control logic.

Abstract: A synchronous switching scheme with adaptive slew control in order to adiabatically charge and discharge a capacitor to recycle charge and generate a boosted voltage on the gate of the synchronous rectifier field effect transistor (FET) is described. In one embodiment, an apparatus includes a synchronous rectifier FET coupled to a transformer, and a secondary-side controller coupled to the synchronous rectifier FET. The secondary-side controller includes a synchronous rectifier gate driver (SRGD) coupled to a gate of the synchronous rectifier FET. The SRGD is to drive the synchronous rectifier FET using the capacitor and an adaptive slew rate, and to adiabatically charge and discharge the capacitor.

Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side integrated circuit (IC controller of the AC-DC converter includes a peak-detector block coupled to detect peak voltages sensed on a SR-SNS pin. The peak-detector block comprises a peak comparator, a sample-and-hold (S/H) circuit, and a DC offset circuit. The peak comparator is coupled to receive a sinusoidal input from the SR-SNS pin. The S/H circuit is coupled to sample the sinusoidal input and to provide a peak sampled voltage. The DC offset voltage circuit is coupled between the output of the S/H circuit and a reference voltage input of the peak comparator to subtract a DC offset voltage from the peak sampled voltage.

Abstract: Techniques for avoiding false negative sense (NSN) detection in a flyback AC-DC converter are described herein. In an example embodiment, a secondary side controller of the AC-DC converter comprises a frequency detector, a negative sense detector, and control logic. The frequency detector is configured to determine a frequency of an input signal from the drain node of a synchronous rectifier (SR) circuit on the secondary side of the AC-DC converter. The negative sense detector is configured to determine a negative voltage of the input signal. The control logic is configured to: enable the negative sense detector, when the frequency of the input signal rises above a frequency threshold value; and turn on the SR circuit to transfer power to the secondary side of the AC-DC converter, when the negative voltage of the input signal falls below a voltage threshold value.

Abstract: A synchronous switching scheme with adaptive slew control in order to adiabatically charge and discharge a capacitor to recycle charge and generate a boosted voltage on the gate of the synchronous rectifier field effect transistor (FET) is described. In one embodiment, an apparatus includes a synchronous rectifier FET coupled to a transformer, and a secondary-side controller coupled to the synchronous rectifier FET. The secondary-side controller includes a synchronous rectifier gate driver (SRGD) coupled to a gate of the synchronous rectifier FET. The SRGD is to drive the synchronous rectifier FET using the capacitor and an adaptive slew rate, and to adiabatically charge and discharge the capacitor.

Abstract: Techniques for avoiding false negative sense (NSN) detection in a flyback AC-DC converter are described herein. In an example embodiment, a secondary side controller of the AC-DC converter comprises a frequency detector, a negative sense detector, and control logic. The frequency detector is configured to determine a frequency of an input signal from the drain node of a synchronous rectifier (SR) circuit on the secondary side of the AC-DC converter. The negative sense detector is configured to determine a negative voltage of the input signal. The control logic is configured to: enable the negative sense detector, when the frequency of the input signal rises above a frequency threshold value; and turn on the SR circuit to transfer power to the secondary side of the AC-DC converter, when the negative voltage of the input signal falls below a voltage threshold value.

Abstract: A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.

Abstract: A secondary-side controller for an AC-DC converter that has a single synchronous rectifier sensing (SR_SNS) terminal, coupled to a synchronous rectifier (SR) of the AC-DC converter, and a voltage divider circuit coupled to the single SR_SNS terminal configured to provide signals to a sensing circuit. The voltage divider includes an active diode, an internal resistive element, and a switch, in which the active diode is configured to control the switch to enable or disable the internal resistive element based on a comparison result of a voltage at the single SR_SNS terminal and a reference voltage.

Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side integrated circuit (IC controller of the AC-DC converter includes a peak-detector block coupled to detect peak voltages sensed on a SR-SNS pin. The peak-detector block comprises a peak comparator, a sample-and-hold (S/H) circuit, and a DC offset circuit. The peak comparator is coupled to receive a sinusoidal input from the SR-SNS pin. The S/H circuit is coupled to sample the sinusoidal input and to provide a peak sampled voltage. The DC offset voltage circuit is coupled between the output of the S/H circuit and a reference voltage input of the peak comparator to subtract a DC offset voltage from the peak sampled voltage.

Abstract: A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.

Abstract: An AC-DC converter with secondary side controller and synchronous rectifier (SR) architecture and method for operating the same are provided. Generally, the controller is implemented as an integrated circuit including a peak-detector module having a peak comparator with a first input coupled to a drain of the SR through a single SR sense (SR-SNS) pin to receive a sinusoidal input. A sample and hold (S/H) circuit with an input coupled to the SR-SNS pin samples the sinusoidal input and holds on an output of thereof a peak sampled voltage received on the input. A direct current (DC) offset voltage coupled between the output of the S/H circuit and the second input of the peak comparator subtracts an DC offset voltage from the peak sampled voltage to compensate for DC offset inaccuracies introduced by the S/H circuit and the peak comparator. Other embodiments are also disclosed.

Abstract: A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.

Abstract: A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.