Abstract: Host device platforms developed based on older ECC (Error Correcting Code) designs may not be equipped to handle the enhanced error correction capabilities in the newer NAND memories. Error correcting memory employing an error threshold representative of the additional capability of the ECC memory allows determining when a fetch has exceeded a safe level of errors to correct. ECC processing compares an error count to the threshold, and if the error count exceeds the threshold of maximum allowable errors, the ECC status module induces an error in the fetched data to alert the host.

Abstract: According to one configuration, computer processor hardware retrieves boot data stored in the non-volatile memory system. The boot data includes executable boot code and corresponding error correction information. The computer processor hardware applies first error correction decoding to the retrieved boot data. In response to detecting an inability to decode the retrieved boot data via application of the first error correction decoding, the computer processor hardware applies second error correction decoding to the retrieved boot data to configure the computer processor hardware.

Abstract: Host device platforms developed based on older ECC (Error Correcting Code) designs may not be equipped to handle the enhanced error correction capabilities in the newer NAND memories. Error correcting memory employing an error threshold representative of the additional capability of the ECC memory allows determining when a fetch has exceeded a safe level of errors to correct. ECC processing compares an error count to the threshold, and if the error count exceeds the threshold of maximum allowable errors, the ECC status module induces an error in the fetched data to alert the host.

Abstract: According to one configuration, computer processor hardware retrieves boot data stored in the non-volatile memory system. The boot data includes executable boot code and corresponding error correction information. The computer processor hardware applies first error correction decoding to the retrieved boot data. In response to detecting an inability to decode the retrieved boot data via application of the first error correction decoding, the computer processor hardware applies second error correction decoding to the retrieved boot data to configure the computer processor hardware.

Abstract: According to one configuration, selection logic analyzes received attributes of particular data to be stored in a non-volatile memory system. Depending on present usage of storage cells in the non-volatile memory system and the attributes of the particular data to be stored, the selection logic selects a mode amongst multiple possible storage modes in which to store the particular data in the non-volatile memory system. Thereafter, the selection logic initiates storage of the particular data in the non-volatile memory system in accordance with the selected storage mode.