Abstract: A molded power semiconductor package includes power semiconductor dies embedded in a mold compound and a lead frame embedded in the mold compound above the power semiconductor dies. A first part of the lead frame includes branches electrically connected to a first load terminal of the power semiconductor dies. A second part of the lead frame is spaced inward from the branches of the first part, and electrically connected to a gate terminal of the power semiconductor dies. The first part of the lead frame has a protrusion that juts out from a first side face of the mold compound to form a first lead of the molded package. A longitudinal axis of the second part of the lead frame intersects the first lead. The second part of the lead frame is physically disconnected from the first lead by a severed region of the lead frame.

Abstract: One aspect of the invention relates to an electronic module comprising a module housing and an electrically conductive connection element. The connection element has a first portion and a second portion, and also a shaft between the first portion and the second portion. The connection element, which is provided with a non-metallic coating in the region of the shaft, is injected together with the coating in the region of the shaft into the module housing, such that the connection element is fixed in the module housing.

Abstract: One aspect of the invention relates to an electronic module comprising a module housing and an electrically conductive connection element. The connection element has a first portion and a second portion, and also a shaft between the first portion and the second portion. The connection element, which is provided with a non-metallic coating in the region of the shaft, is injected together with the coating in the region of the shaft into the module housing, such that the connection element is fixed in the module housing.

Abstract: In a power semiconductor module, a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another. The connection layer has a portion of intermetallic copper-tin phases of at least 90% by weight. For producing such a power semiconductor module the soldering partners and the solder arranged there between are pressed against one another with a predefined pressure and the solder is melted. After termination of a predefined period of time the diffused copper and the tin from the liquid solder form a connection layer comprising intermetallic copper-tin phases, the portion of which is at least 90% by weight of the connection layer created from the solder layer.

Abstract: A die fixing method is disclosed which includes providing a substrate having a metallized surface, forming a joining material on the metallized surface and placing a die alignment member with a plurality of openings on the substrate so that portions of the joining material are exposed through the openings. The method further includes placing a plurality of dies in the openings of the die alignment member with a bottom side of each die in contact with part of the joining material and attaching the plurality of dies to the metallized surface of the substrate at an elevated temperature and pressure, the die alignment member withstanding the elevated temperature and pressure. The die alignment member is removed from the substrate after the plurality of dies are attached to the metallized surface of the substrate.

Abstract: A description is given of a method. In one embodiment the method includes providing a semiconductor chip with semiconductor material being exposed at a first surface of the semiconductor chip. The semiconductor chip is placed over a carrier with the first surface facing the carrier. An electrically conductive material is arranged between the semiconductor chip and the carrier. Heat is applied to attach the semiconductor chip to the carrier.

Abstract: A method of fabricating a semiconductor device. One embodiment provides a metal carrier. A semiconductor chip is provided. A porous layer is produced at a surface of at least one of the carrier and the semiconductor chip. The semiconductor chip is placed on the carrier. The resulting structure is heated until the semiconductor chip is attached to the carrier.

Abstract: In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

Abstract: In a method for producing a power semiconductor arrangement, a dielectric insulation carrier with a top side and a top metallization layer arranged on the top side are provided. Also provided are a semiconductor chip and at least one electrically conductive contact pin, each pin having a first end and an opposite second end. The semiconductor chip is sintered or diffussion soldered to the top metallization layer. Between the first end and the top metallization layer an electrically conductive connection is formed, in which electrically conductive connection material of the contact pin is in direct physical contact with the material of the top metallization layer.

Abstract: A die fixing method is disclosed which includes providing a substrate having a metallized surface, forming a joining material on the metallized surface and placing a die alignment member with a plurality of openings on the substrate so that portions of the joining material are exposed through the openings. The method further includes placing a plurality of dies in the openings of the die alignment member with a bottom side of each die in contact with part of the joining material and attaching the plurality of dies to the metallized surface of the substrate at an elevated temperature and pressure, the die alignment member withstanding the elevated temperature and pressure. The die alignment member is removed from the substrate after the plurality of dies are attached to the metallized surface of the substrate.

Abstract: A device and a method for making a semiconductor device including bonding a first bonding partner to a second bonding partner. The device comprises a lower tool and an upper tool, the upper tool including a plunger having a bottom side facing the lower tool at which bottom side a vacuum is creatable, so that the first bonding partner can be picked up by vacuum from the upper tool and positioned on the second bonding partner.

Abstract: A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface.

Abstract: In a method for producing a power semiconductor arrangement, a dielectric insulation carrier with a top side and a top metallization layer arranged on the top side are provided. Also provided are a semiconductor chip and at least one electrically conductive contact pin, each pin having a first end and an opposite second end. The semiconductor chip is sintered or diffussion soldered to the top metallization layer. Between the first end and the top metallization layer an electrically conductive connection is formed, in which electrically conductive connection material of the contact pin is in direct physical contact with the material of the top metallization layer.

Abstract: In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

Abstract: A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface.

Abstract: A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface.

Abstract: An arrangement for mounting a multiplicity of components (9, 10), particularly with irregular surface topography, on a support (7) using an assembly tool which has a tool substructure (5) and a tool superstructure (6), where the tool substructure (5) is designed to receive the support and the components which are to be mounted thereon, and the tool superstructure (6) has, in addition to an arrangement (11, 12) for transmitting assembly forces, an arrangement for compensating for tilts between the components and the support and/or an arrangement for compensating for irregular surface topologies.

Abstract: An apparatus for connecting a component with a substrate by means of diffusion soldering in a closed evacuated chamber, wherein the component and the substrate to be connected are displaceable separate from one another in the chamber, and the chamber comprises a combined transfer and pressing unit being displaceable between a current position of the component and a current position of the substrate, for placing and pressing the component on the substrate, and the combined transfer and pressing unit comprises a rotatable element, which, in response to the placing and pressing of the component on the substrate, assumes an angle between the normal of a lower side of the component to be connected and a pressing direction of the component, the angle corresponding to an angle between the normal of a surface area of the substrate to be connected and the pressing direction of the component.

Abstract: A description is given of a method. In one embodiment the method includes providing a semiconductor chip with semiconductor material being exposed at a first surface of the semiconductor chip. The semiconductor chip is placed over a carrier with the first surface facing the carrier. An electrically conductive material is arranged between the semiconductor chip and the carrier. Heat is applied to attach the semiconductor chip to the carrier.

Abstract: An apparatus for connecting a component with a substrate by means of diffusion soldering in a closed evacuated chamber, wherein the component and the substrate to be connected are displaceable separate from one another in the chamber, and the chamber comprises a combined transfer and pressing unit being displaceable between a current position of the component and a current position of the substrate, for placing and pressing the component on the substrate, and the combined transfer and pressing unit comprises a rotatable element, which, in response to the placing and pressing of the component on the substrate, assumes an angle between the normal of a lower side of the component to be connected and a pressing direction of the component, the angle corresponding to an angle between the normal of a surface area of the substrate to be connected and the pressing direction of the component.