Abstract: In general, in one aspect, embodiments of the invention relate to a method for generating executable binary. The method includes analyzing a test executable binary generated from source code, wherein the source code comprises a plurality of functions, generating, based on analyzing the test executable binary, a code call tree comprising a plurality of call durations for the plurality of functions, and determining, using the code call tree, a function order of the plurality of functions. The method further includes generating, using the function order, a call tree order map, generating a call tree ordered executable binary using the source code and the call tree order map, and executing the call tree ordered executable binary on a processor.

Abstract: In general, in one aspect, embodiments of the invention relate to a method for generating executable binary. The method includes analyzing a test executable binary generated from source code, wherein the source code comprises a plurality of functions, generating, based on analyzing the test executable binary, a code call tree comprising a plurality of call durations for the plurality of functions, and determining, using the code call tree, a function order of the plurality of functions. The method further includes generating, using the function order, a call tree order map, generating a call tree ordered executable binary using the source code and the call tree order map, and executing the call tree ordered executable binary on a processor.

Abstract: A test coverage tool determines the adequacy of a set of test vectors for a state simulator for exercising logic paths in a logic circuit design. The speed coverage tool generally compares state data from a state simulator and timing data from a timing simulator in order to validate whether a test vector covers a simulated timing path. In architecture, the speed coverage tool includes first logic configured to acquire state data from the logic circuit design that has been produced by a state simulator based upon test vectors. Second logic associated with the tool obtains timing data concerning one or more logic paths of the logic circuit design that has been produced using a timing simulator. Third logic associated with the test coverage tool is configured to determine a transition score by comparing the timing data with the state data. The score is indicative of the adequacy of a set of test vectors.