Abstract: A repair engine for a computing platform is separate from the repeatedly-rewritten storage components for software and firmware. For example, the repair engine may reside in ROM or hardware logic. Through dedicated connections to one or more controllers, the repair engine detects when any of the platform's dual-role ports (e.g., on-the-go USB ports) is connected to a host device. The repair engine responds by opening firmware-independent communication with the host device and supporting the downloading and execution (DnX) of a firmware image from the host. Because the communication is initiated independently of the firmware, even a catastrophic firmware failure is repairable without requiring a user to identify and use a specially modified port.

Abstract: The present techniques include detecting a charger and remote host for a Type-C connector. An apparatus, system, and method are described herein. The apparatus comprises a USB Type-C port and a USB receiver detector. A charger and a remote host are differentiated based on the USB receiver detector.

Abstract: In one embodiment an electronic device includes a processor and at least one universal serial bus (USB) subsystem comprising logic, at least partially including hardware logic, configured to detect a connection from a remote electronic device to a USB port of the electronic device, determine whether the USB port of the electronic device is to act as an upstream facing port or a downstream facing port, and in response to a determination that the USB port of the electronic device is to be configured as an upstream facing port, to implement a port mapping process to map the USB port to one of a device controller or a debug controller. Other embodiments may be described.

Abstract: An apparatus for retimer configuration and control is described herein. The apparatus includes at least one retimer. The is to receive an inband low frequency periodic signal (LFPS), and to send an inband LFPS based pulse width modulation message (LBPM) in response to the inband LFPS. The retimer is configured by decoding the LBPM.

Abstract: A repair engine for a computing platform is separate from the repeatedly-rewritten storage components for software and firmware. For example, the repair engine may reside in ROM or hardware logic. Through dedicated connections to one or more controllers, the repair engine detects when any of the platform's dual-role ports (e.g., on-the-go USB ports) is connected to a host device. The repair engine responds by opening firmware-independent communication with the host device and supporting the downloading and execution (DnX) of a firmware image from the host. Because the communication is initiated independently of the firmware, even a catastrophic firmware failure is repairable without requiring a user to identify and use a specially modified port.

Abstract: Techniques for latency improvement are described herein. The techniques may include an apparatus having a receiver configured to receive transfers over a bus. The transfers include a periodic transfer at a predefined interval, wherein the periodic transfer is associated with a guaranteed bandwidth over the bus. The transfers may also include an asynchronous transfer at any time within the predefined interval. The apparatus may also include logic configured to implement a modified periodic transfer at an interval that is less than the predefined interval, and a modified asynchronous transfer comprising a priority status above the asynchronous transfer.

Abstract: A system, method and apparatus for enabling a closed chassis debug control interface are disclosed. In one embodiment, the system comprises a debug mode control (DCI) unit; a Type-C connector; a Universal Serial Bus (USB) physical (phy) interface coupled to the connector; and interface logic coupled to the DCI unit and the USB phy interface to exchange debug control interface (DCI) signaling between the connector and the DCI unit.

Abstract: An apparatus is described herein. The apparatus includes a Universal Serial Bus (USB) component and a controller interface. The controller interface is to allocate register space for interfacing with the USB component and the USB component is virtualized into multiple instantiations. The apparatus also includes a secure environment, and the secure environment further virtualizes the multiple instantiations such that the multiple instantiations are owned by the secure environment.

Abstract: An apparatus for retimer configuration and control is described herein. The apparatus includes at least one retimer. The is to receive an inband low frequency periodic signal (LFPS), and to send an inband LFPS based pulse width modulation message (LBPM) in response to the inband LFPS. The retimer is configured by decoding the LBPM.

Abstract: The present techniques include detecting a charger and remote host for a Type-C connector. An apparatus, system, and method are described herein. The apparatus comprises a USB Type-C port and a USB receiver detector. A charger and a remote host are differentiated based on the USB receiver detector.

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.

Abstract: Embodiments of the invention utilize a universal serial bus (USB) host controller to traverse an asynchronous data transfer list to identify data transfers to execute. The asynchronous data transfer list may include a plurality of header nodes, each header node to identify data transfers to one of a plurality of devices operatively coupled to an electronic device. The USB host controller may execute an extended sleep mode in response to identifying no data transfers to execute and receiving an indication that the system processor is in a sleep state. The USB host controller may exit the extended sleep mode in response to receiving an indication that the processor is in non-sleep state.

Abstract: A method, apparatus, and system to synchronize multiple host controllers with non-uniform frame rates. The apparatus includes a first host controller, a second host controller, and logic. The first host controller is configured to access memory at a first frame rate. The second host controller is configured to access the memory at a second frame rate which is different from the first frame rate. The logic is coupled to the first and second host controllers to synchronize the memory accesses of the first and second host controllers at a common frame rate. Other embodiments are described.

Abstract: A power reduction proposal for a receiver circuit that adheres to a plurality of defined states and masking logic to mask the output of the squelch receiver. Furthermore, the proposal utilizes and counters to count the various timeout conditions. Consequently, the squelch receiver consumes less power and can be either powered down or periodically enabled to allow for polling.