Abstract: An apparatus to transfer data via a communication link comprises a power bus interface to a power bus of the communication link; at least one data lane transmitter and receiver pair configured to transfer data via a data lane of the communication link; and a power bus data transmitter and receiver pair configured to transfer data via the power bus using pulse width modulation of a data signal on the power bus.

Abstract: In one embodiment, a system on chip includes: at least one core; a plurality of intellectual property (IP) agents coupled to the at least one core; a shared power rail to provide an operating voltage to the plurality of IP agents; and a power controller, in response to an indication that the plurality of IP agents are in an idle state and the at least one core is in an active state, to power down the shared power rail while the at least one core remains in the active state. Other embodiments are described and claimed.

Abstract: Embodiments may include systems and methods for communication including a plurality of controllers and coordination circuitry, to control communication to or from an interface circuitry. The interface circuitry includes a plurality of pins, where a first group of pins of the plurality of pins is for a first communication protocol, and a second group of pins of the plurality of pins is for a second communication protocol. A first controller is coupled to the interface circuitry through the first group of pins, and a second controller is coupled to the interface circuitry through the second group of pins. The coordination circuitry is to select the first controller or the second controller to control communication to or from the interface circuitry. Other embodiments may be described and/or claimed.

Abstract: Embodiments may include systems and methods for communication including a plurality of controllers and coordination circuitry, to control communication to or from an interface circuitry. The interface circuitry includes a plurality of pins, where a first group of pins of the plurality of pins is for a first communication protocol, and a second group of pins of the plurality of pins is for a second communication protocol. A first controller is coupled to the interface circuitry through the first group of pins, and a second controller is coupled to the interface circuitry through the second group of pins. The coordination circuitry is to select the first controller or the second controller to control communication to or from the interface circuitry. Other embodiments may be described and/or claimed.

Abstract: An apparatus to transfer data via a communication link comprises a power bus interface to a power bus of the communication link; at least one data lane transmitter and receiver pair configured to transfer data via a data lane of the communication link; and a power bus data transmitter and receiver pair configured to transfer data via the power bus using pulse width modulation of a data signal on the power bus.

Abstract: A Universal Serial Bus (USB) circuitry of an apparatus is disclosed. In an example, the USB circuitry includes a High Speed (HS) transmitter to transmit data at a first data rate from the apparatus to a component; and a pair of Low Speed/Full speed (LS/FS) receivers to receive data at one or both of a second data rate or a third data rate from the component. In an example, the USB circuitry is to refrain from receiving data from the component at the first data rate.

Abstract: In one embodiment, a system on chip includes: at least one core; a plurality of intellectual property (IP) agents coupled to the at least one core; a shared power rail to provide an operating voltage to the plurality of IP agents; and a power controller, in response to an indication that the plurality of IP agents are in an idle state and the at least one core is in an active state, to power down the shared power rail while the at least one core remains in the active state. Other embodiments are described and claimed.

Abstract: A device including a transceiver to support asymmetrical full duplex communication across a connected medium. The transceiver including a transmission circuit to receive a transmission input and transmit the transmission input via a SuperSpeed data driver and a low frequency periodic signal (LFPS) transmitter over the connected medium, and a receiver circuit coupled to transmission circuit, the receiver circuit to filter a received signal from the connected medium through a low pass filter to an LFPS receiver.

Abstract: Techniques for reducing idle power consumption of a port are described herein. An example method includes determining device presence using a pull-down resistor disposed in a downstream port. The method also includes initiating a low power state of a link between the downstream port and an upstream device. The method also includes disabling the pull-down resistor in response to initiating the low power state.

Abstract: Techniques for reducing idle power consumption of a port are described herein. An example method includes determining device presence using a pull-down resistor disposed in a downstream port. The method also includes initiating a low power state of a link between the downstream port and an upstream device. The method also includes disabling the pull-down resistor in response to initiating the low power state.

Abstract: A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the first frequency, the endpoint device is PCI Express compliant. Otherwise, the computer system initiates another training sequence at a second frequency.

Abstract: A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the first frequency, the endpoint device is PCI Express compliant. Otherwise, the computer system initiates another training sequence at a second frequency.

Abstract: An embodiment of the present invention is an efficient interconnecting bus. A first clock source generates a first clock signal at a first frequency on a link bus line synchronized with first data to be transmitted to a device. The device has a second clock source to generate a second clock signal at a second frequency synchronized with second data when the device transmits the second data. The first and second data each forms a packet being one of a posted, completion, and non-posted packets. The first and second frequencies are independent of each other and bounded within first and second frequency ranges, respectively. A queue structure stores packets used in a credit-based flow control policy.

Abstract: In one embodiment, an apparatus provides a plurality of endpoints, each endpoint corresponding to a function of an emulated device, having at least one buffer to store emulation information corresponding to the emulated device; and logic to perform low level emulation of at least one of the functions corresponding to the plurality of endpoints

Abstract: An embodiment of the present invention is an efficient interconnecting bus. A first clock source generates a first clock signal at a first frequency on a link bus line synchronized with first data to be transmitted to a device. The device has a second clock source to generate a second clock signal at a second frequency synchronized with second data when the device transmits the second data. The first and second data each forms a packet being one of a posted, completion, and non-posted packets. The first and second frequencies are independent of each other and bounded within first and second frequency ranges, respectively. A queue structure stores packets used in a credit-based flow control policy.

Abstract: A method, apparatus, and system to synchronize multiple host controllers with non-uniform frame rates. The apparatus includes a first host controller, a second host controller, and logic. The first host controller is configured to access memory at a first frame rate. The second host controller is configured to access the memory at a second frame rate which is different from the first frame rate. The logic is coupled to the first and second host controllers to synchronize the memory accesses of the first and second host controllers at a common frame rate. Other embodiments are described.

Abstract: A method and apparatus for a race free data transfer algorithm using hardware based polling. One disclosed method transfers information between a target device and a buffer which is one of a set of buffers. The buffer is pointed to by a current buffer value stored in a controller. The current buffer value is adjusted to point to a next buffer if the current buffer value is different than a last buffer value. One of the set of buffers is serviced utilizing either the current buffer value or the last buffer value from the controller.

Abstract: A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the first frequency, the endpoint device is PCI Express compliant. Otherwise, the computer system initiates another training sequence at a second frequency.