Patents by Inventor Karthick Rajamani

Karthick Rajamani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10223153
    Abstract: Utilizing a computing device to determine and enforce limits on cloud computing containers transmitting data over a network. A determination is made of total container time remaining available for a first container to execute in a computing environment, the first container utilizing one or more processor threads executing on a computing device. Processor packet transmission time is determined for processing and transmission of a packet or a batch of packets via a network stack associated with the computing device by the one or more processor threads utilized by the first container. An updated total container time remaining for the first container is calculated, accounting for the processor packet transmission time. The updated total container time remaining is enforced by descheduling all processor threads utilized by the first container if the updated total container time remaining is insufficient.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Wesley M. Felter, Junaid Khalid, Karthick Rajamani, Eric Rozner, Cong Xu
  • Publication number: 20190004579
    Abstract: A computer controls power distribution. The computing system determines a topography for a power delivery system that powers a group of computing devices. The computing system determines a number of worker programs for a pool of worker programs based on the topography. The computing system generates the pool of worker programs. The pool of worker programs includes both the number of worker programs and a number of back-up worker programs. The computing system generates a number of power management tasks to manage power consumption through one or more power elements included in the topography of the power delivery system. The computing system sends one or more power management tasks to a worker program included in the pool of worker programs.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 3, 2019
    Inventors: Malcolm S. Allen-Ware, Kanak B. Agarwal, Charles Lefurgy, Guillermo J. Silva, Thomas W. Keller, Karthick Rajamani, Yang Li, Ramakrishnan Rajamony
  • Publication number: 20180267585
    Abstract: A mechanism is provided for enforcing power caps within a power consumption device with multiple power supplies. Utilizing a minimum power error value from a set of error values, the minimum power error value is multiplied by a factor k to translate the minimum power error value to an internal power error value. The internal minimum power error value is multiplied by a number of working power supply units (M) of the power consumption device, resulting in an internal minimum power error value for multiple power supply units. The internal minimum power error value for the multiple power supply units is summed with a present power cap value thereby forming a summed power cap value. Responsive to the summed power cap value being between a power cap maximum and a power cap minimum, the computing load is throttled using the summed power cap value.
    Type: Application
    Filed: March 15, 2017
    Publication date: September 20, 2018
    Inventors: Malcolm S. Allen-Ware, Charles R. Lefurgy, Yang Li, Karthick Rajamani, Guillermo J. Silva
  • Publication number: 20180267597
    Abstract: A mechanism is provided for power capping power consumption devices with multiple power supplies. A set of power supplies supplying power to a power consumption device having stranded power is determined. A power budget of one or more power supplies in the set of power supplies is adjusted to match a power budget of a power supply in the set of power supplies with a limiting power budget among the power budgets computed for each power supply in the set of power supplies. Responsive to identifying at least one power supply in the one or more other power supplies of one or more different power consumption devices having an initially allocated power budget below their corresponding demand, at least a portion of the stranded power is allocated to the power budget of the at least one power supply.
    Type: Application
    Filed: March 15, 2017
    Publication date: September 20, 2018
    Inventors: Malcolm S. Allen-Ware, Charles R. Lefurgy, Yang Li, Karthick Rajamani, Guillermo J. Silva
  • Publication number: 20180260330
    Abstract: Dynamically allocating cache in a multi-tenant infrastructure includes monitoring cache usage for multiple workloads in a multi-tenant processing infrastructure to determine a workload phase. A baseline performance level per workload is determined. The baseline performance level is dependent upon the workload phase. The workloads for each tenant are categorized based on cache utilization and the cache is allocated to each workload based on the baseline performance level, cache utilization, and system wide cache capacity.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 13, 2018
    Inventors: Wesley M. Felter, Alexandre P. Ferreira, Karthick Rajamani, Juan C. Rubio, Cong Xu
  • Patent number: 10067523
    Abstract: A data center energy management (DCEM) server configures a power supply in the data center. The DCEM server sums input alternating current (AC) power of the power supply to a total AC power of the data center, wherein the total AC power of the data center is a sum of AC power of a plurality of power supplies. The DCEM server sums output direct current (DC) power of the power supply to a total DC power of the data center and reports a ratio of total AC power to total DC power as data center power conversion efficiency. The DCEM server sets a preset power supply efficiency threshold. The DCEM server determines that a real-time power efficiency level is below the power supply efficiency threshold. The DCEM server, responsive to a determination that real-time power efficiency level is below the power supply efficiency threshold, may remedy the power supply.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Wael R. El-Essawy, Karthick Rajamani, Juan C. Rubio
  • Patent number: 10025619
    Abstract: Utilizing a computing device to determine and enforce limits on cloud computing containers transmitting data over a network. A determination is made of total container time remaining available for a first container to execute in a computing environment, the first container utilizing one or more processor threads executing on a computing device. Processor packet transmission time is determined for processing and transmission of a packet or a batch of packets via a network stack associated with the computing device by the one or more processor threads utilized by the first container. An updated total container time remaining for the first container is calculated, accounting for the processor packet transmission time. The updated total container time remaining is enforced by descheduling all processor threads utilized by the first container if the updated total container time remaining is insufficient.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Wesley M. Felter, Junaid Khalid, Karthick Rajamani, Eric Rozner, Cong Xu
  • Publication number: 20180151246
    Abstract: Examples of techniques for a built-in self-test (BIST) for embedded spin-transfer torque magnetic random access memory (STT-MRAM) are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: initiating, by a processor, a BIST for the STT-MRAM; performing, by the processor, an error-correcting code (ECC) test for a portion of the STT-MRAM; responsive to the ECC test not being passed, determining whether a maximum signal is reached; responsive to the maximum signal not being reached, increasing the signal and performing the ECC test again; and responsive to the maximum signal being reached, determining that the portion of the STT-MRAM is bad.
    Type: Application
    Filed: November 29, 2016
    Publication date: May 31, 2018
    Inventors: Michael B. Healy, Hillery C. Hunter, Janani Mukundan, Karthick Rajamani, Saravanan Sethuraman
  • Patent number: 9952651
    Abstract: A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory, where the memory includes a program configured to adjust a frequency of a multi-core processor. The operations include determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The operations also include calculating a switching current by subtracting the leakage current from the total current and calculating an effective switching capacitance based at least in part on the switching current. The operations also include calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Malcolm S. Allen-Ware, Michael S. Floyd, Joshua D. Friedrich, Charles R. Lefurgy, Kirk D. Peterson, Karthick Rajamani, Srinivasan Ramani, Todd J. Rosedahl, Gregory S. Still, Brian W. Thompto, Victor Zyuban
  • Publication number: 20180101217
    Abstract: A method and apparatus for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for the inhibited processor cores, and then uninhibiting the processor cores requesting exit from the idle state.
    Type: Application
    Filed: December 7, 2017
    Publication date: April 12, 2018
    Inventors: Malcolm S. ALLEN-WARE, Charles R. LEFURGY, Karthick RAJAMANI, Todd J. ROSEDAHL, Guillermo J. SILVA, Gregory S. STILL, Victor ZYUBAN
  • Patent number: 9934079
    Abstract: A system, and computer usable program product for fast remote communication and computation between processors are provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: April 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Bruce Carter, Elmootazbellah Nabil Elnozahy, Ahmed Gheith, Eric Van Hansbergen, Karthick Rajamani, William Evan Speight, Lixin Zhang
  • Patent number: 9933836
    Abstract: A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited and non-idle processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for both the inhibited and the non-idle processor cores, and then uninhibiting the processor cores requesting exit from the idle state.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: April 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Malcolm S. Allen-Ware, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Guillermo J. Silva, Gregory S. Still, Victor Zyuban
  • Patent number: 9880599
    Abstract: A mechanism is provided for throttling power utilized by a set of power consumption devices using priority-aware power capping. Responsive to unassigned power budget remaining in the overall power budget after a minimum power budget value has been assigned to the child device based on an associated priority of the child device, an additional power budget value equal to a remaining priority-based exposed power demand value of the child device is assigned to the child device in response to the remaining unassigned power budget being greater than or equal to the remaining priority-based demanded power value thereby forming a total power budget for the child device. Responsive to design limitations of power distribution equipment in the data processing system or contractual limits of the data processing system being reached, a throttling is implemented by each child device based on the total power budget assigned to the child device.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Thomas W. Keller, Jr., Charles R. Lefurgy, Yang Li, Karthick Rajamani, Samuel W. Shanks, Guillermo J. Silva, Eddie L. Smith, James Yanes
  • Publication number: 20180006925
    Abstract: A device may monitor a communication between network devices for an error associated with the communication. The device may detect the error associated with the communication between the network devices. The device may perform a comparison of an error metric and a threshold error metric. The error metric may be associated with the error. The device may determine whether the comparison indicates that the error metric satisfies the threshold error metric. The device may identify a source of the error using a loopback test based on determining whether the comparison indicates that the error metric satisfies the threshold error metric. The device may provide error source information based on identifying the source of the error. The error source information may identify the source of the error.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Amit BOHRA, Rahul Yashwant KULKARNI, Khalid Akhtar ANSARI, Karthick RAJAMANI
  • Patent number: 9823680
    Abstract: A data center energy management (DCEM) server configures a power supply in the data center. The DCEM server sums input alternating current (AC) power of the power supply to a total AC power of the data center, wherein the total AC power of the data center is a sum of AC power of a plurality of power supplies. The DCEM server sums output direct current (DC) power of the power supply to a total DC power of the data center and reports a ratio of total AC power to total DC power as data center power conversion efficiency. The DCEM server sets a preset power supply efficiency threshold. The DCEM server determines that a real-time power efficiency level is below the power supply efficiency threshold. The DCEM server, responsive to a determination that real-time power efficiency level is below the power supply efficiency threshold, may remedy the power supply.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Wael R. El-Essawy, Karthick Rajamani, Juan C. Rubio
  • Patent number: 9811150
    Abstract: A method for managing a processor, the processor comprising a common supply rail and processor cores being connected to the common supply rail, wherein each processor core comprises a core unit, wherein the method comprises detecting idle state exits indicated by the core units; and delaying a command execution of at least one of the core units indicating an idle state exit when the number of idle state exits exceeds a predetermined threshold idle state exit number may reduce voltage droops due to several processor cores leaving the idle state at the same time.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: November 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Alan James Drake, Michael Stephen Floyd, Charles Robert Lefurgy, Karthick Rajamani, Tobias Webel
  • Patent number: 9778726
    Abstract: A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The method also includes calculating a switching current by subtracting the leakage current from the total current. The method also includes calculating an effective switching capacitance based at least in part on the switching current. The method also includes calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: October 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Malcolm S. Allen-Ware, Michael S. Floyd, Joshua D. Friedrich, Charles R. Lefurgy, Kirk D. Peterson, Karthick Rajamani, Srinivasan Ramani, Todd J. Rosedahl, Gregory S. Still, Brian W. Thompto, Victor Zyuban
  • Patent number: 9733692
    Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Shawn P. Authement, John C. Elliott, Charles R. Lefurgy, J. Carlos A. Pratt, Karthick Rajamani, David B. Whitworth
  • Patent number: 9733691
    Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Shawn P. Authement, John C. Elliott, Charles R. Lefurgy, J. Carlos A. Pratt, Karthick Rajamani, David B. Whitworth
  • Patent number: 9733685
    Abstract: A method, system, and computer program product for controlling power supplied to a processor is disclosed. A voltage regulator is set to a first voltage regulator set point, wherein the first voltage regulator set point provides a first load line for operation of the processor. A change in an operation of the processor from a first operating condition along the first load line to a second operating condition along the first load line is determined. The voltage regulator is the set to a second voltage regulator set point and the processor is operated at a third operating condition on a second load line corresponding to the second voltage regulator set point.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles R. Lefurgy, Karthick Rajamani, Richard F. Rizzolo, Malcolm S. Allen-Ware