Abstract: Systems, circuits, and chips for hardening a latch/flip-flop circuit against soft errors caused by alpha and neutron radiation are provided. As an example, a latch/flip-flop circuit including a switch to selectively couple a capacitor to first and second storage nodes during a hold phase is disclosed.

Abstract: Systems, circuits, and chips for hardening a latch/flip-flop circuit against soft errors caused by alpha and neutron radiation are provided. As an example, a latch/flip-flop circuit including a switch to selectively couple a capacitor to first and second storage nodes during a hold phase is disclosed.

Abstract: A circuit for steering charges generated from ionization radiation away from a latch includes charge steering transistors operating in strong inversion. The charge steering transistors are electrically coupled to other transistors in stacked inverters within the latch. During normal operation, the charge steering transistors are turned on when the other transistors being coupled to are turned off. The charge steering transistors may reduce the negative impact of ionization radiation on the operation of the latch.

Abstract: According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.

Abstract: A hysteresis-based logic element design for improved soft error rate with low area/performance overhead. In one embodiment, a hysteresis inverter block including one or more pairs of inverters can be coupled to a logic element to adjust a switching threshold of the logic element.

Abstract: According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.

Abstract: A hysteresis-based logic element design for improved soft error rate with low area/performance overhead. In one embodiment, a hysteresis inverter block including one or more pairs of inverters can be coupled to a logic element to adjust a switching threshold of the logic element.

Abstract: According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.

Abstract: According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.

Abstract: A disclosed embodiment is a data retention flip flop comprising master and slave circuits that are configured to be turned off when a single sleep mode signal is activated. The disclosed embodiment also comprises an always-on balloon circuit coupled to the master circuit, where the always-on balloon circuit includes a common sub-circuit shared with the master circuit. The master circuit writes into the always-on balloon circuit when the single sleep mode signal is activated, and the master circuit reads from the always-on balloon circuit when the single sleep mode signal is deactivated. The always-on balloon circuits comprises high threshold voltage transistors, while the slave circuit comprises low threshold voltage transistors. The master and slave circuits have no leakage current, or substantially no leakage current, after the single sleep mode signal is activated.

Abstract: A disclosed embodiment is a low leakage data retention flip flop comprising a master circuit for retaining data during sleep mode, wherein the master circuit is configured to receive a reduced supply voltage during the sleep mode. The flip flop includes a slave circuit having low threshold voltage transistors, where the slave circuit is turned off during the sleep mode. In various embodiments, the master circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. Similarly, the slave circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. To begin the sleep mode, the master circuit receives a reduced supply voltage and the slave circuit is coupled to ground and is thus turned off. During the sleep mode, the slave circuit experiences virtually no leakage current, and the master circuit experiences a reduced leakage current.

Abstract: A disclosed embodiment is a data retention flip flop comprising master and slave circuits that are configured to be turned off when a single sleep mode signal is activated. The disclosed embodiment also comprises an always-on balloon circuit coupled to the master circuit, where the always-on balloon circuit includes a common sub-circuit shared with the master circuit. The master circuit writes into the always-on balloon circuit when the single sleep mode signal is activated, and the master circuit reads from the always-on balloon circuit when the single sleep mode signal is deactivated. The always-on balloon circuits comprises high threshold voltage transistors, while the slave circuit comprises low threshold voltage transistors. The master and slave circuits have no leakage current, or substantially no leakage current, after the single sleep mode signal is activated.

Abstract: A disclosed embodiment is a low leakage data retention flip flop comprising a master circuit for retaining data during sleep mode, wherein the master circuit is configured to receive a reduced supply voltage during the sleep mode. The flip flop includes a slave circuit having low threshold voltage transistors, where the slave circuit is turned off during the sleep mode. In various embodiments, the master circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. Similarly, the slave circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. To begin the sleep mode, the master circuit receives a reduced supply voltage and the slave circuit is coupled to ground and is thus turned off. During the sleep mode, the slave circuit experiences virtually no leakage current, and the master circuit experiences a reduced leakage current.