Abstract: A data transmission system includes a first integrated circuit. The first integrated circuit includes a first mixing terminal coupled to a first power supply voltage terminal at a point internal to the first integrated circuit, a first return terminal, a first resistor having a first terminal coupled to the first mixing terminal, and a second terminal for providing a first mixed voltage, and a second resistor having a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to the first return terminal.

Abstract: A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only in response to the memory receiving a read command.

Abstract: Domain specialty instructions may be generated for performing text analysis tasks. An input text may be received for performing a text analysis task. A domain specialty may be identified for the input text. Specialty domain identifiers may be inserted as part of generating instructions to perform the text analysis task using a pre-trained large language model fine-tuned to a domain that includes multiple domain specialties. The pre-trained large language model may perform the text analysis task on the input text using the generated instructions. A result of the text analysis tsk performed on the input text may be provided.

Abstract: Disclosed herein is a medical system (100, 300, 500) comprising a memory (110) storing machine executable instructions (120) and a B0 field estimation module (126); and a computational system (106). Execution of the machine executable instructions causes the computational system to receive (200) an initial magnetic resonance image (122) that comprises a magnitude component and is descriptive of a first region (326) of interest of a subject (118).

Abstract: Pairs of text collections are obtained. An individual pair comprises (a) a source text collection which includes a first group of text sequences and (b) an annotated analysis result of the source text collection, comprising a second group of text sequences and a set of evidence mappings generated by an evidence mapping model. An evidence mapping indicates, for a particular text sequence of the second group, another text sequence of the first group which provides evidence for the particular text sequence. A quality metric of the model is obtained using an automated evaluation methodology in which a question is generated from the particular text sequence, and an analysis of a pair of answers (including an answer generated using an evidence mapping) to the question is performed. The quality metric is provided via a programmatic interface.

Abstract: Domain specialty instructions may be generated for performing text analysis tasks. An input text may be received for performing a text analysis task. One or more domain entities may be extracted from the input text using a machine learning model trained to recognize entities of a domain in a given text. The one or more domain entities may be inserted as part of generating instructions to perform the text analysis task using a pre-trained machine learning model fine-tuned to the domain. The pre-trained machine learning model may be caused to perform the text analysis task using the generated instructions and a result of the text analysis task may be provided.

Abstract: A receiver is trained for receiving a signal over a data bus. A volatile memory is commanded over the data bus to place a selected pulse-amplitude modulation (PAM) driver in a mode with a designated steady output level. At a receiver circuit coupled to the selected PAM driver, a respective reference voltage associated with the designated steady output level is swept through a range of voltages and the respective reference voltage is compared to a voltage received from the PAM driver to determine a respective voltage level received from the PAM driver.

Abstract: An integrated circuit includes a first terminal for receiving a data signal, a second terminal for receiving an external reference voltage, a receiver, and a reference voltage generation circuit. The receiver is powered by a power supply voltage with respect to ground and has a first input coupled to the first terminal, a second input for receiving a shared reference voltage, and an output for providing a data input signal. The reference voltage generation circuit is coupled to the second terminal and receives the power supply voltage. The reference voltage generation circuit is operable to form the shared reference voltage by mixing noise from the power supply voltage and noise from the second terminal.

Abstract: A method for receiving a multi-level error signal having more than two logic levels includes oversampling the multi-level error signal to provide sampled symbols, wherein a first level of the multi-level error signal indicates no error, and second and third levels of the multi-level error signal indicate first and second error conditions, respectively. The sampled signals are de-serialized to provide sets of symbols. A start of a symbol period is determined in response to detecting that a given sample is different from a prior sample, and the prior sample indicates no error. The sets of symbols are filtered to provide corresponding output symbols based on the start.

Abstract: A driver circuit includes a feed-forward equalization (FFE) circuit. The FFE circuit receives a plurality of pulse-amplitude modulation (PAM) symbol values to be transmitted at one of multiple PAM levels. The FFE circuit includes a first partial lookup table, one or more additional partial lookup tables, and an adder circuit. The first partial lookup table contains partial finite impulse-response (FIR) values and indexed based on a current PAM symbol value, a precursor PAM symbol value, and a postcursor PAM symbol value. The one or more additional partial lookup tables each contain partial FIR values and indexed based on a respective additional one or more of the PAM symbol values. The adder circuit adds results of lookups from the first partial lookup table and the additional partial lookup tables to produce an output value.

Abstract: A driver circuit includes a feed-forward equalization (FFE) circuit. The FFE circuit receives a plurality of pulse-amplitude modulation (PAM) symbol values to be transmitted at one of multiple PAM levels. The FFE circuit includes a first partial lookup table, one or more additional partial lookup tables, and an adder circuit. The first partial lookup table contains partial finite impulse-response (FIR) values and indexed based on a current PAM symbol value, a precursor PAM symbol value, and a postcursor PAM symbol value. The one or more additional partial lookup tables each contain partial FIR values and indexed based on a respective additional one or more of the PAM symbol values. The adder circuit adds results of lookups from the first partial lookup table and the additional partial lookup tables to produce an output value.

Abstract: A data processor, system, method, integrated circuit are provided which update timing values for accessing a memory to compensate for voltage and temperature (VT) drift during operation. The method includes performing a link retraining sequence for a plurality of DQ lanes of the memory bus and determining a first phase offset based on the link retraining. The method includes calculating a second offset based on the first offset, applying the second offset to a plurality of command CA lanes of the memory bus.

Abstract: A data processor, system, method, integrated circuit are provided which update timing values for accessing a memory to compensate for voltage and temperature (VT) drift during operation. The method includes performing a link retraining sequence for a plurality of DQ lanes of the memory bus and determining a first phase offset based on the link retraining. The method includes calculating a second offset based on the first offset, applying the second offset to a plurality of command CA lanes of the memory bus.

Abstract: Various examples relate to a firmware apparatus (10), firmware device, firmware method, and computer program for a computer system (100) comprising processing circuitry (105), and to a corresponding computer system (100). The firmware apparatus (10) comprises an interface (12) for accessing functionality of the firmware apparatus (10) from an operating system of the computer system (100). The firmware apparatus (10) comprises control circuitry (14), configured to identify one or more processing functionalities being supported by the processing circuitry (105) of the computer system (100), provide information on the one or more processing functionalities via the interface (12) to a user mode interface of the operating system of the computer system (100), and provide access to the one or more processing functionalities for application programs being executed in the operation system, the access being based on the information on the one or more processing functionalities provided to the user mode interface.

Abstract: A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, with a length of the initial toggling state and a length of the final toggling state are based on values in a mode register.

Abstract: The disclosed computer-implemented method includes providing, by a reference clock circuit, a clock signal for a clock-triggered element triggered by the clock signal and modulating, by a frequency modulation circuit, a frequency of the clock signal. The method also includes inserting, by a phase compensation circuit, a phase compensation offset to the modulated clock signal in a manner that compensates for a phase error produced by modulating the frequency of the clock signal. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A voltage regulator includes an input power supply node, an output regulated power supply node, a flipped voltage follower circuit, and a compensation capacitor. The flipped voltage follower circuit includes an output transistor configured as a common-source amplifier circuit. A source terminal of the output transistor is coupled to the input power supply node and a drain terminal of the output transistor is coupled to the output regulated power supply node. The flipped voltage follower circuit includes a folded cascode feedback circuit. The folded cascode feedback circuit includes a folding node. The folded cascode feedback circuit is configured to receive an output regulated voltage on the output regulated power supply node and to provide a feedback signal to a gate terminal of the output transistor. The compensation capacitor is coupled to the output regulated power supply node and the folding node.

Abstract: A method for receiving a multi-level error signal having more than two logic levels includes oversampling the multi-level error signal to provide sampled symbols, wherein a first level of the multi-level error signal indicates no error, and second and third levels of the multi-level error signal indicate first and second error conditions, respectively. The sampled signals are de-serialized to provide sets of symbols. A start of a symbol period is determined in response to detecting that a given sample is different from a prior sample, and the prior sample indicates no error. The sets of symbols are filtered to provide corresponding output symbols based on the start.

Abstract: Detailed herein are examples of hybrid (heterogenous) performance monitoring unit enumeration. In some examples, a processor supports an instruction that enumerates performance monitoring unit enumeration. For example, the processor comprises decoder circuitry to decode an instance of a single instruction, the single instruction to include a field for an opcode; and execution circuitry to execute the decoded instruction according to the opcode to return the processor identification and feature information including an enumeration of heterogenous performance monitoring unit capabilities.

Abstract: A memory system includes a PHY embodied on an integrated circuit, the PHY coupling to a memory over conductive traces on a substrate. The PHY includes a reference clock generation circuit providing a reference clock signal to the memory, a first group of driver circuits providing CA signals to the memory, and a second group of driver circuits providing DQ signals to the memory. A plurality of the conductive traces which carry the DQ signals are constructed with a length longer than that of conductive traces carrying the reference clock signal in order to reduce an effective insertion delay associated with coupling the reference clock signal to latch respective incoming DQ signals.