Abstract: Techniques for managing digital messages to and from a proxy message address are disclosed. A system receives a message directed to a particular destination address. The system replaces any source address included in the message with a proxy address. When the system receives a reply to the message, the reply is directed to the proxy address. The system analyzes message data to identify a target address for the reply message. The system identifies contextual data associated with the reply message. The system transmits the reply message, and the contextual data, to the target address.

Abstract: Techniques for managing digital messages to and from a shared mailbox are disclosed. A system receives a message directed to a shared mailbox. The system analyzes contextual data in the message to identify a set of users with access to the shared mailbox who are recipients of the message. The system performs notification operations to notify different users with access to the shared mailbox of different messages. Notification operations include sending a notification to a particular communications platform, such as email, instant message, or text, that a message in the shared mailbox is associated with the recipient, tagging the message in the shared mailbox with names of recipients associated with the message, and/or categorizing the messages in the shared mailbox according to users.

Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.

Abstract: A radio receiver device is disclosed. The radio receiver device is configured to receive a radio signal comprising a data packet, said data packet comprising a first portion comprising an encoded bit sequence and including information specific to the data packet and a second portion comprising an encoded bit sequence and comprising corresponding information specific to the data packet. The radio receiver device is configured to calculate a correlation metric using the first portion and the second portion; and to estimate a carrier frequency offset between the radio signal and the radio receiver device using the correlation metric.

Abstract: A receiver apparatus for receiving an OFDM radio signal comprising a first plurality of subcarrier-symbols, modulated on a corresponding plurality of subcarriers, and a second plurality of subcarrier-symbols, modulated on the corresponding plurality of subcarriers, to generate first and second bit sequences, the first bit sequence being an interleaved version of the second bit sequence according to a predetermined interleave function. Soft-output decoder logic generates a first soft-bit sequence for the first plurality of subcarrier-symbols, and a second soft-bit sequence for the second plurality of subcarrier-symbols. Combiner logic combines the soft-bit sequences, with the soft-bit sequences either both in an interleaved state or both in a non-interleaved state, by combining a respective soft-bit having a bit position in the first soft-bit sequence with a respective soft-bit having a same bit position in the second soft-bit sequence.

Abstract: A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.

Abstract: A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.

Abstract: A direct down-conversion (DDC) front end receiver includes first Q-channel that filters a sum of PRBS and baseband quadrature signals to generate a first filtered quadrature signal, a second Q-channel that filters a difference of the baseband and PRBS signals to generate a second filtered quadrature signal, a first I-channel and a second I-channel, Q-path and I-path PRBS cancellation blocks for cancelling corresponding PRBS components from sum of first and second filtered quadrature signals and sum of first and second filtered inphase signals respectively, Q-path and I-path sum filter estimation blocks for estimating quadrature and inphase sum filter responses. An IQ mismatch compensation filter estimate and tracking block estimates IQ mismatch compensation filter response from estimated quadrature and inphase sum filter responses, and an IQ mismatch compensation filter filters the modified inphase signal with the IQ mismatch compensation filter response, to generate a filter compensated inphase signal.

Abstract: A direct down-conversion (DDC) front end receiver includes first Q-channel that filters a sum of PRBS and baseband quadrature signals to generate a first filtered quadrature signal, a second Q-channel that filters a difference of the baseband and PRBS signals to generate a second filtered quadrature signal, a first I-channel and a second I-channel, Q-path and I-path PRBS cancellation blocks for cancelling corresponding PRBS components from sum of first and second filtered quadrature signals and sum of first and second filtered inphase signals respectively, Q-path and I-path sum filter estimation blocks for estimating quadrature and inphase sum filter responses. An IQ mismatch compensation filter estimate and tracking block estimates IQ mismatch compensation filter response from estimated quadrature and inphase sum filter responses, and an IQ mismatch compensation filter filters the modified inphase signal with the IQ mismatch compensation filter response, to generate a filter compensated inphase signal.

Abstract: A system can include a close-in tone control configured to detect a set of close-in tones of an interleaved analog to digital converter (IADC) signal and output a trigger signal in response to the detection. The system can also include a close-in tone mismatch estimator configured to determine a correlation and a power estimate for the set of close-in tones in the IADC signal in response to the trigger signal.

Abstract: A system can include a close-in tone control configured to detect a set of close-in tones of an interleaved analog to digital converter (IADC) signal and output a trigger signal in response to the detection. The system can also include a close-in tone mismatch estimator configured to determine a correlation and a power estimate for the set of close-in tones in the IADC signal in response to the trigger signal.