Patents by Inventor Karthik Kumar

Karthik Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10608956
    Abstract: Described herein are devices and techniques for distributing application data. A device can communicate with one or more hardware switches. The device can receive, from a software stack, a multicast message including a constraint that indicates how application data is to be distributed. The constraint including a listing of the set of nodes and a number of nodes to which the application data is to be distributed. The device may receive, from the software stack, the application data for distribution to a plurality of nodes. The plurality of nodes being a subset of the set of nodes equaling the number of nodes. The device may select the plurality of nodes from the set of nodes. The device also may distribute a copy of the application data to the plurality of nodes based on the constraint. Also described are other embodiments.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Francesc Cesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Narayan Ranganathan
  • Patent number: 10598443
    Abstract: Embodiments of a thermal management system are provided herein. In some embodiments, a thermal management system may include a base plate; and a plurality of three dimensional fins coupled to the base, wherein each of the plurality of three dimensional fins comprises a first portion extending away from the base in a first direction and a second a portion extending away from the first portion in a second direction different from the first direction.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: March 24, 2020
    Assignee: General Electric Company
    Inventors: Karthik Kumar Bodla, Hendrik Pieter Jacobus de Bock
  • Patent number: 10599579
    Abstract: Cache on a persistent memory module is dynamically allocated as a prefetch cache or a write back cache to prioritize read and write operations to a persistent memory on the persistent memory module based on monitoring read/write accesses and/or user-selected allocation.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Karthik Kumar, Francesc Guim Bernat, Benjamin Graniello, Thomas Willhalm, Mustafa Hajeer
  • Patent number: 10592359
    Abstract: A system and method for handling one or more dependency services hosted by one or more dependency servers for an upstream service hosted by an administrative server in a distributed computer architecture is provided. The present invention provides for identifying any abnormality in the behavior of the dependency services on the basis of metric values associated with service-parameters of said dependency services. Further, the resiliency services are enabled in order to handle one or more faltering dependency services based on the faulty metric values associated with the service-parameters. Yet further, the one or more faltering dependency services are continuously monitored, and one or more resiliency services are withdrawn once the fault in said dependency services is resolved. Yet further, the present invention provides a conversational bot interface for managing the administrative server and associated dependency services.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: March 17, 2020
    Assignee: COGNIZANT TECHNOLOGY SOLUTIONS INDIA PVT. LTD.
    Inventors: Senthil Ramaswamy Sankarasubramanian, Deepak Panneerselvam, Karthik Kumar
  • Patent number: 10584923
    Abstract: A support form defining a longitudinal axis is provided. The support form includes a first section, a second substantially solid section, and at least one flow feature form. The first section includes a plurality of unit cells of a first material joined together to form a lattice. The second section includes a second material and surrounds the first section. The at least one flow feature form is defined in the second section and is configured to generate a flow feature on a heat exchanger tube formed by plating the support form.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: March 10, 2020
    Assignee: General Electric Company
    Inventors: Hendrik Pieter Jacobus de Bock, Karthik Kumar Bodla, William Dwight Gerstler, James Albert Tallman, Konrad Roman Weeber
  • Publication number: 20200076682
    Abstract: Technologies for providing multi-tenant support in edge resources using edge channels include a device that includes circuitry to obtain a message associated with a service provided at the edge of a network. Additionally, the circuitry is to identify an edge channel based on metadata associated with the message. The edge channel has a predefined amount of resource capacity allocated to the edge channel to process the message. Further, the circuitry is to determine the predefined amount of resource capacity allocated to the edge channel and process the message using the allocated resource capacity for the identified edge channel.
    Type: Application
    Filed: March 28, 2019
    Publication date: March 5, 2020
    Inventors: Francesc Guim Bernat, Karthik Kumar, Benjamin Graniello, Timothy Verrall, Andrew J. Herdrich, Rashmin Patel, Monica Kenguva, Brinda Ganesh, Alexander Vul, Ned M. Smith, Suraj Prabhakaran
  • Patent number: 10547680
    Abstract: Systems, methods, and apparatuses for range protection. In some embodiments, an apparatus comprises at least one monitoring circuit to monitor for memory accesses to an address space and take action upon a violation to the address space, wherein the action is one of generating a notification to a node that requested the monitor, generating the wrong request, generate a notification in a specific context of the home node, and generating a notification in a node that has ownership of the address space; at least one a protection table to store an identifier of the address space; and at least one hardware core to execute an instruction to enable the monitoring circuit.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Robert G. Blankenship
  • Publication number: 20200026575
    Abstract: Methods, apparatus, systems and machine-readable storage media of an edge computing device which is enabled to access and select the use of local or remote acceleration resources for edge computing processing is disclosed. In an example, an edge computing device obtains first telemetry information that indicates availability of local acceleration circuitry to execute a function, and obtains second telemetry that indicates availability of a remote acceleration function to execute the function. An estimated time (and cost or other identifiable or estimateable considerations) to execute the function at the respective location is identified. The use of the local acceleration circuitry or the remote acceleration resource is selected based on the estimated time and other appropriate factors in relation to a service level agreement.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Inventors: Francesc Guim Bernat, Karthik Kumar, Ned M. Smith, Thomas Willhalm, Timothy Verrall
  • Patent number: 10541942
    Abstract: Technologies for accelerating edge device workloads at a device edge network include a network computing device which includes a processor platform that includes at least one processor which supports a plurality of non-accelerated function-as-a-service (FaaS) operations and an accelerated platform that includes at least one accelerator which supports a plurality of accelerated FaaS (AFaaS) operation. The network computing device is configured to receive a request to perform a FaaS operation, determine whether the received request indicates that an AFaaS operation is to be performed on the received request, and identify compute requirements for the AFaaS operation to be performed. The network computing device is further configured to select an accelerator platform to perform the identified AFaaS operation and forward the received request to the selected accelerator platform to perform the identified AFaaS operation. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Anil Rao, Suraj Prabhakaran, Mohan Kumar, Karthik Kumar
  • Publication number: 20200007460
    Abstract: There is disclosed in one example a communication apparatus, including: a telemetry interface; a management interface; and an edge gateway configured to: identify diverted traffic, wherein the diverted traffic includes traffic to be serviced by an edge microcloud configured to provide a plurality of services; receive telemetry via the telemetry interface; use the telemetry to anticipate a future per-service demand within the edge microcloud; compute a scale for a resource to meet the future per-service demand; and operate the management interface to instruct the edge microcloud to perform the scale before the future per-service demand occurs.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Mark A. Schmisseur, Timothy Verrall
  • Publication number: 20190391855
    Abstract: Technologies for providing efficient data access in an edge infrastructure include a compute device comprising circuitry configured to identify pools of resources that are usable to access data at an edge location. The circuitry is also configured to receive a request to execute a function at an edge location. The request identifies a data access performance target for the function. The circuitry is also configured to map, based on a data access performance of each pool and the data access performance target of the function, the function to a set of the pools to satisfy the data access performance target.
    Type: Application
    Filed: September 6, 2019
    Publication date: December 26, 2019
    Inventors: Francesc Guim Bernat, Karthik Kumar, Suraj Prabhakaran, Timothy Verrall, Thomas Willhalm, Mark Schmisseur
  • Publication number: 20190384516
    Abstract: The present disclosure relates to a dynamically composable computing system comprising a computing fabric with a plurality of different disaggregated computing hardware resources having respective hardware characteristics. A resource manager has access to the respective hardware characteristics of the different disaggregated computing hardware resources and is configured to assemble a composite computing node by selecting one or more disaggregated computing hardware resources with respective hardware characteristics meeting requirements of an application to be executed on the composite computing node. An orchestrator is configured to schedule the application using the assembled composite computing node.
    Type: Application
    Filed: August 1, 2019
    Publication date: December 19, 2019
    Inventors: Francesc Guim Bernat, Karthik Kumar, John Chun Kwok LEUNG, Mark Schmisseur, Thomas Willhalm
  • Publication number: 20190384837
    Abstract: A group of cache lines in cache may be identified as cache lines not to be flushed to persistent memory until all cache line writes for the group of cache lines have been completed.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 19, 2019
    Inventors: Karthik KUMAR, Francesc GUIM BERNAT, Thomas WILLHALM, Mark A. SCHMISSEUR, Benjamin GRANIELLO
  • Patent number: 10509728
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receive a request from a core, the request associated with a memory operation to read or write data, and the request comprising a first address and an offset, the first address to identify a memory location of a memory. Embodiments include performing a first iteration of a memory indirection operation comprising reading the memory at the memory location to determine a second address based on the first address, and determining a memory resource based on the second address and the offset, the memory resource to perform the memory operation for the computing resource or perform a second iteration of the memory indirection operation.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 17, 2019
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Mark Schmisseur, Thomas Willhalm
  • Patent number: 10509738
    Abstract: An extension of node architecture and proxy requests enables a node to expose memory computation capability to remote nodes. A remote node can request execution of an operation by a remote memory computation resource, and the remote memory computation resource can execute the request locally and return the results of the computation. The node includes processing resources, a fabric interface, and a memory subsystem including a memory computation resource. The local execution of the request by the memory computation resource can reduce latency and bandwidth concerns typical with remote requests.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Narayan Ranganathan, Pete D. Vogt
  • Patent number: 10481958
    Abstract: An embodiment of a semiconductor package apparatus may include technology to track a modification to a processor cache line, and set an indicator to indicate if the modification relates to a transaction. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: November 19, 2019
    Assignee: Intel IP Corporation
    Inventors: Thomas Willhalm, Karthik Kumar
  • Patent number: 10448126
    Abstract: Technologies for dynamically allocating tiers of disaggregated memory resources include a compute device. The compute device is to obtain target performance data, determine, as a function of target performance data, memory tier allocation data indicative of an allocation of disaggregated memory sleds to tiers of performance, in which one memory sled of one tier is to act as a cache for another memory sled of a subsequent tier, send the memory tier allocation data and the target performance data to the corresponding memory sleds through a network, receive performance notification data from one of the memory sleds in the tiers, and determine, in response to receipt of the performance notification data, an adjustment to the memory tier allocation data.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Ginger H. Gilsdorf, Karthik Kumar, Thomas Willhalm, Francesc Guim Bernat, Mark A. Schmisseur
  • Publication number: 20190305646
    Abstract: An electrical winding topology having a core and a plurality of windings is provided. The plurality of windings is operatively coupled to the core, where at least one of the plurality of windings includes an evaporator section and a condenser section. Further, at least a portion of one or more of the plurality of windings includes heat pipes.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 3, 2019
    Inventors: Karthik Kumar Bodla, Samir Armando Salamah
  • Publication number: 20190281132
    Abstract: Technologies for managing telemetry and sensor data on an edge networking platform are disclosed. According to one embodiment disclosed herein, a device monitors telemetry data associated with multiple services provided in the edge networking platform. The device identifies, for each of the services and as a function of the associated telemetry data, one or more service telemetry patterns. The device generates a profile including the identified service telemetry patterns.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 12, 2019
    Inventors: Ramanathan Sethuraman, Timothy Verrall, Ned M. Smith, Thomas Willhalm, Brinda Ganesh, Francesc Guim Bernat, Karthik Kumar, Evan Custodio, Suraj Prabhakaran, Ignacio Astilleros Diez, Nilesh K. Jain, Ravi Iyer, Andrew J. Herdrich, Alexander Vul, Patrick G. Kutch, Kevin Bohan, Trevor Cooper
  • Publication number: 20190278631
    Abstract: Data management for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow a device, such as an endpoint or client device, or another edge resource, to specify criteria for managing data originating from the device and stored in an edge resource, and extends the storage and memory controllers to manage data in accordance with the criteria, including removing stored data that no longer satisfies the criteria. The criteria includes a temporal hint to specify a time after which the data can be removed, a physical hint to specify a list of edge resources outside of which the data can be removed, an event-based hint to specify an event after which the data can be removed, and a quality of service condition to modify the time specified in the temporal hint based on a condition, such as memory and storage capacity of the edge resource in which the data is managed.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 12, 2019
    Inventors: Francesc GUIM BERNAT, Ramanathan SETHURAMAN, Karthik KUMAR, Mark A. SCHMISSEUR, Brinda GANESH