Abstract: In various examples, techniques for performing software code verification are described. Systems and methods are disclosed for generating, using intermediate code and user input, a call graph that represents source code for software. For instance, the call graph represents at least functions (e.g., internal functions, external functions, etc.) associated with the software, calls (e.g., direct calls, call pointers, etc.) between the functions, and register information associated with the functions (e.g., variables used by the functions, assembly code used by the functions, etc.). The systems and methods may further use the call graph to perform software code verification by verifying rules from design specifications for the software and/or rules from various certification standards.

Abstract: Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more functions to be performed in response to one or more errors from one or more accelerators within a heterogeneous processor.

Abstract: Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more operations in a sequence of operations to be performed by one or more accelerators within a heterogeneous processor.

Abstract: Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more functions to be performed in response to one or more errors from one or more accelerators within a heterogeneous processor.

Abstract: Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to transfer information between memory of two or more accelerators.

Abstract: Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more memory regions to store error information from one or more accelerators within a heterogeneous processor.

Abstract: In various examples, techniques for performing software code verification are described. Systems and methods are disclosed for generating, using intermediate code and user input, a call graph that represents source code for software. For instance, the call graph represents at least functions (e.g., internal functions, external functions, etc.) associated with the software, calls (e.g., direct calls, call pointers, etc.) between the functions, and register information associated with the functions (e.g., variables used by the functions, assembly code used by the functions, etc.). The systems and methods may further use the call graph to perform software code verification by verifying rules from design specifications for the software and/or rules from various certification standards.

Abstract: Apparatuses, systems, and techniques to perform multi-architecture execution graphs. In at least one embodiment, a parallel processing platform, such as compute uniform device architecture (CUDA) generates multi-architecture execution graphs comprising a plurality of software kernels to be performed by one or more processor cores having one or more processor architectures.