Patents by Inventor Karthik Raj

Karthik Raj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250127479
    Abstract: A mechanism for automatically generating and ranking M-mode lines for generating or defining M-mode data usable to assess fetal heart activity, e.g. determine a fetal heart rate. A region of interest, containing a fetal heart, in a sequence of ultrasound images is identified. The region of interest is used to define the position of each of a plurality of M-mode lines, e.g. anatomical M-mode lines. A quality measure of each M-mode line is determined based on M-mode data generated for each M-mode line, and the quality measures are then used to rank the M-mode lines.
    Type: Application
    Filed: June 22, 2022
    Publication date: April 24, 2025
    Inventors: Soumabha Bhowmick, Karthik Krishnan, Karthik Raj Katipally, Giridhar Narasapura Rajagopalaiah, Celine Firtion, Subhendu Seth, Pallavi Vajinepalli, David Nigel Roundhill, Matthew Rielly
  • Publication number: 20250088407
    Abstract: This disclosure describes an event bus system that, as part of an inter-network facilitation system, can generate and distribute network events for self-service event requests utilizing a network event data streaming platform. For example, the disclosed systems can utilize a network event data streaming platform that includes specialized network components, such as a batch distribution data lake and an event fanning platform. The disclosed systems can utilize the batch distribution data lake to distribute long-retention network events for high-latency event requests. Additionally, the disclosed systems can utilize the event fanning platform to generate low-latency fanned data streams from short-retention network events for low-latency event requests.
    Type: Application
    Filed: July 15, 2024
    Publication date: March 13, 2025
    Inventors: Sherin Thomas, Jayanth Bharadwaj, Arun Mehta, Karthik Raj, Bhashinee Garg
  • Patent number: 12040933
    Abstract: This disclosure describes an event bus system that, as part of an inter-network facilitation system, can generate and distribute network events for self-service event requests utilizing a network event data streaming platform. For example, the disclosed systems can utilize a network event data streaming platform that includes specialized network components, such as a batch distribution data lake and an event fanning platform. The disclosed systems can utilize the batch distribution data lake to distribute long-retention network events for high-latency event requests. Additionally, the disclosed systems can utilize the event fanning platform to generate low-latency fanned data streams from short-retention network events for low-latency event requests.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: July 16, 2024
    Assignee: Chime Financial, Inc.
    Inventors: Sherin Thomas, Jayanth Bharadwaj, Arun Mehta, Karthik Raj, Bhashinee Garg
  • Publication number: 20240231961
    Abstract: This disclosure describes an event fanning system that, as part of an inter-network facilitation system, can generate and provide consumer application data streams using an event fanning platform. For example, the disclosed systems can utilize an event fanning platform to generate application-specific data streams for providing requested network events. The disclosed systems can further tie a consumer application data stream to a lifecycle of the consumer application requesting one or more network events included within the data stream. Additionally, the disclosed systems can utilize the event fanning platform to generate updated consumer application data streams based on modifications to consumer applications.
    Type: Application
    Filed: January 11, 2023
    Publication date: July 11, 2024
    Inventors: Sherin Thomas, Arun Mehta, Karthik Raj, Jayanth Bharadwaj
  • Publication number: 20240195675
    Abstract: This disclosure describes an event bus system that, as part of an inter-network facilitation system, can generate and distribute network events for self-service event requests utilizing a network event data streaming platform. For example, the disclosed systems can utilize a network event data streaming platform that includes specialized network components, such as a batch distribution data lake and an event fanning platform. The disclosed systems can utilize the batch distribution data lake to distribute long-retention network events for high-latency event requests. Additionally, the disclosed systems can utilize the event fanning platform to generate low-latency fanned data streams from short-retention network events for low-latency event requests.
    Type: Application
    Filed: December 9, 2022
    Publication date: June 13, 2024
    Inventors: Sherin Thomas, Jayanth Bharadwaj, Arun Mehta, Karthik Raj, Bhashinee Garg
  • Publication number: 20240086567
    Abstract: This disclosure describes a schema modification system that, as part of an inter-network facilitation system, can intelligently generate and update payload schemas for maintaining compatibility across changing network components. For example, the disclosed systems utilize custom tooling to detect changes in component versions and to update payload schemas to translate digital payloads between components that require different payload formats (e.g., due to an update to one component or another). In some cases, the disclosed systems can utilize a code generator to generate a payload conversion code from a payload schema and can implement the payload conversion code to convert a digital payload from a source format to a target format (e.g., to pass from a source component to a target component). The disclosed systems can also utilize schema annotations that accompany a payload schema to perform various functions, including removing sensitive information and identifying third-party systems.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 14, 2024
    Inventors: Bhashinee Garg, Nikita Uraltsev, Arun Mehta, Sherin Thomas, Karthik Raj, Jayanth Bharadwaj, Lucas Kacher
  • Publication number: 20210011979
    Abstract: A battery emulator can include an active voltage controlled device (VCD), one or more selectable RC filter banks, and a controller coupled to the active VCD and the one or more selectable RC filter banks. The controller may be configured to sense a load on the battery emulator and control the active VCD so as to implement a low frequency battery transfer function derived from a battery model. The controller may be further configured to control the one or more selectable RC filter banks so as to implement a high frequency battery transfer function derived from the battery model. The controller may further include a gas gauge emulation module configured to interface with a gas gauge interface of a device under test. The controller may further include a communications module configured to interface with a test host.
    Type: Application
    Filed: July 12, 2019
    Publication date: January 14, 2021
    Inventors: Doug MacKay, Karthik Raj Kaliannan, Daniyal Sattarian
  • Patent number: 8364857
    Abstract: A computing device includes a low power auxiliary processor, such as a processor on a wireless card or sub-system, which is able to takeover processing in place of the computing device's central processing unit (CPU). Operating the computing device on the auxiliary processor draws less power from the computing device battery, enabling extended operation in an auxiliary processor mode. When in this mode, the auxiliary processor controls peripherals and provides the system functionality while the CPU is deactivated, such as in “off,” “standby” or “sleep” modes. In the auxiliary processor mode, the computing device can accomplish useful tasks, such as sending/receiving electronic mail, displaying electronic documents and accessing a network while drawing minimal power from the battery. Transitions between the normal operating mode and auxiliary processor mode may be transparent to users. Such a computer may display instant on, always on and always connected operating features.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: January 29, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: James Pyers, George Wiley, James J. Willkie, Brian Steele, Apul Nahata, Karthik Raj Kaliannan
  • Publication number: 20110055434
    Abstract: A computing device includes a low power auxiliary processor, such as a processor on a wireless card or sub-system, which is able to takeover processing in place of the computing device's central processing unit (CPU). Operating the computing device on the auxiliary processor draws less power from the computing device battery, enabling extended operation in an auxiliary processor mode. When in this mode, the auxiliary processor controls peripherals and provides the system functionality while the CPU is deactivated, such as in “off,” “standby” or “sleep” modes. In the auxiliary processor mode, the computing device can accomplish useful tasks, such as sending/receiving electronic mail, displaying electronic documents and accessing a network while drawing minimal power from the battery. Transitions between the normal operating mode and auxiliary processor mode may be transparent to users. Such a computer may display instant on, always on and always connected operating features.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 3, 2011
    Inventors: James PYERS, George WILEY, James J. WILLKIE, Brian STEELE, Apul NAHATA, Karthik Raj KALIANNAN