Patents by Inventor Karthik Rajagopal

Karthik Rajagopal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230341528
    Abstract: A system comprises a photosensor and a controller. A first photoemitter transmits light onto objects at first height, a second photoemitter onto objects at second, lower height, and a third photoemitter onto objects at third, lowest height. The controller causes one of the photoemitters to transmit modulated light and the photosensor to receive reflections from a scene. The controller determines a depth map for the corresponding height based on phase differences between the transmitted and reflected light. In some examples, the system is included in an autonomous robot's navigation system. The navigation system identifies overhanging objects at the robot's top from the depth map at the first height, obstacles in the navigation route from a second depth map at the second height, and cliffs and drop-offs in the ground surface in front of the robot from the third depth map at the third height.
    Type: Application
    Filed: June 28, 2023
    Publication date: October 26, 2023
    Inventors: Yichang Wang, Karthik Rajagopal Ganapathy, Raja Reddy Patukuri
  • Patent number: 11733360
    Abstract: A time of flight (ToF) system comprises three photoemitters, a photosensor, and a controller. The first photoemitter transmits light onto objects at first height, the second photoemitter onto objects at second, lower height, and the third photoemitter onto objects at third, lowest height. The controller causes one of the photoemitters to transmit modulated light and the photosensor to receive reflections from the scene. The controller determines a depth map for the corresponding height based on phase differences between the transmitted and reflected light. In some examples, the ToF system is included in an autonomous robot's navigation system. The navigation system identifies overhanging objects at the robot's top from the depth map at the first height, obstacles in the navigation route from the depth map at the second height, and cliffs and drop-offs in the ground surface in front of the robot from the depth map at the third height.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: August 22, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yichang Wang, Karthik Rajagopal Ganapathy, Raja Reddy Patukuri
  • Publication number: 20230099807
    Abstract: A camera system includes a camera, an illumination source, a first light sensor having a first light sensor output, and a second light sensor having a second light sensor output. A processor has inputs coupled to the camera's output, the first light sensor output, and the second light sensor output, and the processor has an output coupled to the input of the illumination source. The processor receives a first light signal from the first light sensor output, receive a second light signal from the second light sensor output, determine a first weight for the first light signal and a second weight for the second light signal based on a difference between the first and second light signals, calculate a weighted average of the first and second light signals using the first and second weights, and determine whether to turn on the illumination source based on the weighted average.
    Type: Application
    Filed: May 27, 2022
    Publication date: March 30, 2023
    Inventor: Karthik Rajagopal GANAPATHY
  • Publication number: 20230061912
    Abstract: In an example, a system includes a surface including one or more light sources and one or more sensors. The system also includes a dome structure configured to cover the surface. The system includes an output port on the surface configured to provide light from the one or more light sources to a device under test. The system also includes a controller coupled to the one or more sensors and configured to adjust the one or more light sources based at least in part on feedback from a sensor.
    Type: Application
    Filed: January 18, 2022
    Publication date: March 2, 2023
    Inventor: Karthik Rajagopal Ganapathy
  • Publication number: 20230049989
    Abstract: Embodiments herein generally relate to an electronic system and a method of monitoring and providing feedback to adjust and improve the allocation of, use of, and/or control over one or more physical spaces. Embodiments of the disclosure can provide an electronic system and method that allows a user to reserve a work space within a room or building. The methods disclosed herein can include inputting one or more desk preferences into one or more processing devices, receiving, at one or more electronic devices, the desk preferences, determining whether a suitable desk matching the desk preferences is available, and generating an alert on the one or more electronic devices regarding the availability of the suitable desk.
    Type: Application
    Filed: August 10, 2021
    Publication date: February 16, 2023
    Inventors: Gregory FRANC DE FERRIERE, Henry LEVAK, Aleksandr KIROV, Trevor Alan RUSH, Karthik RAJAGOPAL
  • Publication number: 20230050116
    Abstract: Embodiments herein generally relate to an electronic system and a method of monitoring and providing feedback to adjust and improve the allocation of, use of, and/or control over one or more physical spaces. Embodiments of the disclosure can provide an electronic system and method that allows a user to reserve a work space within a room or building. The methods disclosed herein can include inputting one or more desk preferences into one or more processing devices, receiving, at one or more electronic devices, the desk preferences, determining whether a suitable desk matching the desk preferences is available, and generating an alert on the one or more electronic devices regarding the availability of the suitable desk.
    Type: Application
    Filed: August 10, 2021
    Publication date: February 16, 2023
    Inventors: Gregory FRANC DE FERRIERE, Henry LEVAK, Aleksandr KIROV, Trevor Alan RUSH, Karthik RAJAGOPAL
  • Patent number: 11170009
    Abstract: The present invention discloses a system and a method for resource data classification and management. In operation, the present invention provides for evaluating a deployment probability score for each incoming data-record based on previous data-records. Further, a match score of each incoming data-record is computed. Furthermore, each incoming data-record is analyzed to determine a bench period associated with each incoming data-record. Yet further, the present invention, categorizes the incoming data-records into two or more categories based on corresponding deployment probability score, match score and bench period. A deployment opportunity index is generated for each incoming data-record representing the categories and corresponding probability score, match score and bench period, providing an upfront indication of deploy-ability of an incoming data-record. Finally, the present invention provides for generating a list of recommendations for each data-record.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: November 9, 2021
    Assignee: COGNIZANT TECHNOLOGY SOLUTIONS INDIA PVT. LTD.
    Inventors: Swaminath Venkataraman, Dinesh Suresh, Karthik Rajagopal, Girivas Vaidyanathan, Anand Kabra, Arunava Bhattacharjee, Ramesh Srinivasan, Shreshth Raitani, Suresh Ramanathan Aylur, Ankit Sharma, Giridhar Sampathkumar
  • Publication number: 20210124748
    Abstract: The present invention discloses a system and a method for resource data classification and management. In operation, the present invention provides for evaluating a deployment probability score for each incoming data-record based on previous data-records. Further, a match score of each incoming data-record is computed. Furthermore, each incoming data-record is analyzed to determine a bench period associated with each incoming data-record. Yet further, the present invention, categorizes the incoming data-records into two or more categories based on corresponding deployment probability score, match score and bench period. A deployment opportunity index is generated for each incoming data-record representing the categories and corresponding probability score, match score and bench period, providing an upfront indication of deploy-ability of an incoming data-record. Finally, the present invention provides for generating a list of recommendations for each data-record.
    Type: Application
    Filed: January 24, 2020
    Publication date: April 29, 2021
    Inventors: Swaminath Venkataraman, Dinesh Suresh, Karthik Rajagopal, Girivas Vaidyanathan, Anand Kabra, Arunava Bhattacharjee, Ramesh Srinivasan, Shreshth Raitani, Suresh Ramanathan Aylur, Ankit Sharma, Giridhar Sampathkumar
  • Publication number: 20200386873
    Abstract: A time of flight (ToF) system comprises three photoemitters, a photosensor, and a controller. The first photoemitter transmits light onto objects at first height, the second photoemitter onto objects at second, lower height, and the third photoemitter onto objects at third, lowest height. The controller causes one of the photoemitters to transmit modulated light and the photosensor to receive reflections from the scene. The controller determines a depth map for the corresponding height based on phase differences between the transmitted and reflected light. In some examples, the ToF system is included in an autonomous robot's navigation system. The navigation system identifies overhanging objects at the robot's top from the depth map at the first height, obstacles in the navigation route from the depth map at the second height, and cliffs and drop-offs in the ground surface in front of the robot from the depth map at the third height.
    Type: Application
    Filed: October 24, 2019
    Publication date: December 10, 2020
    Inventors: Yichang Wang, Karthik Rajagopal Ganapathy, Raja Reddy Patukuri
  • Patent number: 9823688
    Abstract: A method for designing a clock tree is disclosed. In one embodiment, a preliminary clock tree design for an integrated circuit (IC) is processed. The clock tree includes a root node, a number of intermediate levels, and a leaf level that is coupled to a number of clocked circuits. Clock gating circuits are placed at the leaf level of the clock tree, and at least some of the intermediate levels. Processing the preliminary clock tree design includes ensuring that an equal number of clock gating circuits are coupled between each leaf level clock gating circuit and the root node. After processing the preliminary clock tree design, clock tree synthesis is performed by executing a clock tree synthesis tool on a computer system to generate a synthesized clock tree design.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: November 21, 2017
    Assignee: Apple Inc.
    Inventors: Karthik Rajagopal, Narayanan V. Thondugulam, Rahul Sharma
  • Patent number: 9817937
    Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: November 14, 2017
    Assignee: Apple Inc.
    Inventors: Shingo Suzuki, Karthik Rajagopal, Bo Tang
  • Patent number: 9607125
    Abstract: Embodiments of an electromigration (EM) check scheme to reduce a pessimism on current density limits by checking wire context. This methodology, in an embodiment, includes applying existing electronic design automation (EDA) flows and tools to identify potentially-failing wires based on a worst-case EM check using conservative foundry current density limits. A more accurate, context-specific check can be performed on the potentially-failing wires to eliminate one or more of the potentially-failing wires if those wires do not experience worst-case conditions and meet current density limits based on an actual context of those wires. A designer can correct remaining wires which are not eliminated by the context-specific check.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: March 28, 2017
    Assignee: Apple Inc.
    Inventors: Antonietta Oliva, Karthik Rajagopal, Manoj Gopalan, Mini Nanua, Sambasivan Narayan
  • Publication number: 20170041589
    Abstract: A time-of-flight (TOF) camera system for correcting non-linearity in phase-to-depth measurements. The TOF camera system includes a module to simulate movement of a target object by generating delays between modulation signals emitted from a transmitter and demodulation signals received by a sensor. For each delay, the TOF system calculates and stores a phase output corresponding to a simulated distance of the target object. The TOF camera may consult the stored data during normal operation to perform in-field calibration.
    Type: Application
    Filed: August 8, 2016
    Publication date: February 9, 2017
    Inventors: Bharat PATIL, Jagannathan VENKATARAMAN, Karthik RAJAGOPAL
  • Publication number: 20160299524
    Abstract: A method for designing a clock tree is disclosed. In one embodiment, a preliminary clock tree design for an integrated circuit (IC) is processed. The clock tree includes a root node, a number of intermediate levels, and a leaf level that is coupled to a number of clocked circuits. Clock gating circuits are placed at the leaf level of the clock tree, and at least some of the intermediate levels. Processing the preliminary clock tree design includes ensuring that an equal number of clock gating circuits are coupled between each leaf level clock gating circuit and the root node. After processing the preliminary clock tree design, clock tree synthesis is performed by executing a clock tree synthesis tool on a computer system to generate a synthesized clock tree design.
    Type: Application
    Filed: April 8, 2015
    Publication date: October 13, 2016
    Inventors: Karthik Rajagopal, Narayanan V. Thondugulam, Rahul Sharma
  • Patent number: 9323071
    Abstract: Laser speckle reduction using a passive diffuser. A diffuser for reducing laser speckle is disclosed comprising a diffuser having a colloid configured for placement in a light path of a coherent light source. The colloid exhibits Brownian motion. The diffuser can be formed of transparent plates containing the colloid. In a system for illumination, a coherent source of light outputting a light beam along a light path is provided; and a diffuser for reducing laser speckle effects is placed in the light path, the diffuser comprising a colloid disposed in a container that is transparent to the light beam output by the coherent source. A method includes illuminating a photosensitive sensor, comprising transmitting a coherent light from a light source through a diffuser comprising a colloid and directing the light from the diffuser onto the photosensitive sensor. Additional embodiments are disclosed.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: April 26, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bharath Patil, Karthik Rajagopal, Subhash Chandra Venkata Sadhu
  • Publication number: 20160085900
    Abstract: In an embodiment, a methodology for designing an integrated circuit that attempts to improve power efficiency is provided. The methodology includes simulating the design under one or more power stimuli, where the power stimuli are known to cause high power consumption (e.g. in previous designs of the integrated circuit, the power stimuli may have caused power consumption). A set of nets within the integrated circuit may be identified that have the highest activity in the simulation (e.g. the highest amount of switching). The methodology may include providing data to the routing tool that is to route the nets in the integrated circuit. The data may indicate constraints for the set of nets, to help reduce dynamic power on these nets. Power efficiency of the integrated circuit may be improved if the routing tool is able to honor the constraints.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 24, 2016
    Inventors: Amit Chandra, Karthik Rajagopal, Muthukumaravelu Velayoudame, Praveen Bhutani, Sunil Mehta
  • Patent number: 9292648
    Abstract: In an embodiment, a methodology for designing an integrated circuit that attempts to improve power efficiency is provided. The methodology includes simulating the design under one or more power stimuli, where the power stimuli are known to cause high power consumption (e.g. in previous designs of the integrated circuit, the power stimuli may have caused power consumption). A set of nets within the integrated circuit may be identified that have the highest activity in the simulation (e.g. the highest amount of switching). The methodology may include providing data to the routing tool that is to route the nets in the integrated circuit. The data may indicate constraints for the set of nets, to help reduce dynamic power on these nets. Power efficiency of the integrated circuit may be improved if the routing tool is able to honor the constraints.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: March 22, 2016
    Assignee: Apple Inc.
    Inventors: Amit Chandra, Karthik Rajagopal, Muthukumaravelu Velayoudame, Praveen Bhutani, Sunil Mehta
  • Publication number: 20160034630
    Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.
    Type: Application
    Filed: October 12, 2015
    Publication date: February 4, 2016
    Inventors: Shingo Suzuki, Karthik Rajagopal, Bo Tang
  • Patent number: 9189586
    Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: November 17, 2015
    Assignee: Apple Inc.
    Inventors: Shingo Suzuki, Karthik Rajagopal, Bo Tang
  • Publication number: 20150078001
    Abstract: Laser speckle reduction using a passive diffuser. A diffuser for reducing laser speckle is disclosed comprising a diffuser having a colloid configured for placement in a light path of a coherent light source. The colloid exhibits Brownian motion. The diffuser can be formed of transparent plates containing the colloid. In a system for illumination, a coherent source of light outputting a light beam along a light path is provided; and a diffuser for reducing laser speckle effects is placed in the light path, the diffuser comprising a colloid disposed in a container that is transparent to the light beam output by the coherent source. A method includes illuminating a photosensitive sensor, comprising transmitting a coherent light from a light source through a diffuser comprising a colloid and directing the light from the diffuser onto the photosensitive sensor. Additional embodiments are disclosed.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 19, 2015
    Inventors: Bharath Patil, Karthik Rajagopal, Subhash Chandra Venkata Sadhu