Patents by Inventor Karthik Ramanan
Karthik Ramanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11891047Abstract: A method for having a vehicle follow a desired curvature path is provided. The vehicle has at least one differential with a differential lock connected to at least one driven wheel axle of the vehicle. The method includes providing information regarding state of the differential lock, the state being either that the differential lock is activated or unlocked, and when the differential lock is activated, calculating a yaw moment of the vehicle caused by the differential lock; and compensating for a deviation from the desired curvature path caused by the yaw moment such that a resulting steering angle is equal to or less than a maximum allowed steering angle of the vehicle. The compensation is a feed forward compensation.Type: GrantFiled: October 22, 2018Date of Patent: February 6, 2024Assignee: VOLVO TRUCK CORPORATIONInventors: Leo Laine, Karthik Ramanan Vaidyanathan
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Patent number: 11742012Abstract: A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.Type: GrantFiled: May 28, 2021Date of Patent: August 29, 2023Assignee: NXP USA, INC.Inventors: Karthik Ramanan, Jon Scott Choy, Padmaraj Sanjeevarao
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Patent number: 11691609Abstract: A control arrangement for a vehicle motion system including a braking function, comprising motion actuators with one or more brake actuators pertaining to the braking function, a first vehicle motion management controller (VMM1) and a second vehicle motion management controller (VMM2), forming a redundant assembly to control the braking function, wherein, in riding conditions, the first vehicle motion management controller controls the brake actuators with a current nominal expected braking performance, while the second vehicle motion management controller (VMM2) is in a waiting-to-operate mode, the control arrangement comprising a hot swap functionality in which the second vehicle motion management controller (VMM2) is configured to take over control of the brake actuators from the first vehicle motion management controller, with the current nominal expected braking performance, in a short time period (SWT) less than one second, preferably less than 0.5 second, preferably less than 0.Type: GrantFiled: May 3, 2018Date of Patent: July 4, 2023Assignee: Volvo Truck CorporationInventors: Leo Laine, Lionel Farres, Christian Oscarsson, Leon Henderson, Johanna Majqvist, Jose Vilca, Kristoffer Tagesson, Karthik Ramanan Vaidyanathan, Nicolas Soulier
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Patent number: 11521692Abstract: A memory includes a plurality of one-time programmable (OTP) memory cells, wherein each OTP memory cell includes a corresponding storage element capable of being in a permanently blown state or non-blown state. In the non-blown state, the corresponding storage element is capable of being in a low conductive state (LCS) or high conductive state (HCS). Control circuitry is configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells, direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and, after the write circuitry applies the voltage differential across the corresponding storage element, direct read circuitry to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.Type: GrantFiled: March 18, 2021Date of Patent: December 6, 2022Assignee: NXP USA, Inc.Inventors: Jon Scott Choy, Jacob T. Williams, Karthik Ramanan, Padmaraj Sanjeevarao, Maurits Mario Nicolaas Storms
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Patent number: 11521665Abstract: A non-volatile memory includes resistive cells, write circuitry, and write detect circuitry. Each resistive cell has a resistive storage element and is coupled to a corresponding first column line and corresponding second column line. The write circuitry is configured to provide a write current through a resistive storage element of a selected resistive memory cell during a write operation based on an input data value. The write detect circuitry is configured to generate a reference voltage using a voltage at the corresponding first column line coupled to the selected resistive memory cell at an initial time of the write operation, and, during the write operation, after the initial time, provide a write detect signal based on a comparison between the voltage at the corresponding first column line coupled to the selected resistive memory cell and the reference voltage, wherein the input data value is based on the write detect signal.Type: GrantFiled: May 4, 2021Date of Patent: December 6, 2022Assignee: NXP USA, Inc.Inventors: Jacob T. Williams, Gilles Joseph Maurice Muller, Karthik Ramanan, Jon Scott Choy
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Publication number: 20220383925Abstract: A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.Type: ApplicationFiled: May 28, 2021Publication date: December 1, 2022Inventors: Karthik Ramanan, Jon Scott Choy, Padmaraj Sanjeevarao
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Publication number: 20220358982Abstract: A non-volatile memory includes resistive cells, write circuitry, and write detect circuitry. Each resistive cell has a resistive storage element and is coupled to a corresponding first column line and corresponding second column line. The write circuitry is configured to provide a write current through a resistive storage element of a selected resistive memory cell during a write operation based on an input data value. The write detect circuitry is configured to generate a reference voltage using a voltage at the corresponding first column line coupled to the selected resistive memory cell at an initial time of the write operation, and, during the write operation, after the initial time, provide a write detect signal based on a comparison between the voltage at the corresponding first column line coupled to the selected resistive memory cell and the reference voltage, wherein the input data value is based on the write detect signal.Type: ApplicationFiled: May 4, 2021Publication date: November 10, 2022Inventors: Jacob T. Williams, Gilles Joseph Maurice Muller, Karthik Ramanan, Jon Scott Choy
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Publication number: 20220301647Abstract: A memory includes a plurality of one-time programmable (OTP) memory cells, wherein each OTP memory cell includes a corresponding storage element capable of being in a permanently blown state or non-blown state. In the non-blown state, the corresponding storage element is capable of being in a low conductive state (LCS) or high conductive state (HCS). Control circuitry is configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells, direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and, after the write circuitry applies the voltage differential across the corresponding storage element, direct read circuity to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.Type: ApplicationFiled: March 18, 2021Publication date: September 22, 2022Inventors: Jon Scott Choy, Jacob T. Williams, Karthik Ramanan, Padmaraj Sanjeevarao, Maurits Mario Nicolaas Storms
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Patent number: 11348628Abstract: A memory includes virtual ground circuitry configured to generate a virtual ground voltage (greater than zero volts) at a virtual ground node, a memory array of resistive memory cells in which each resistive memory cell includes a select transistor and a resistive storage element and is coupled to a first column line of a plurality of first column lines, and a first decoder configured to select a set of first column lines for a memory read operation from a selected set of the resistive memory cells. The memory includes read circuitry, and a first column line multiplexer configured to couple each selected first column line of the set of first column lines to the read circuitry during the memory read operation, and configured to couple each unselected first column line of the plurality of first column lines to the virtual ground node during the memory read operation.Type: GrantFiled: September 25, 2020Date of Patent: May 31, 2022Assignee: NXP USA, Inc.Inventors: Karthik Ramanan, Jon Scott Choy
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Publication number: 20220101902Abstract: A memory includes virtual ground circuitry configured to generate a virtual ground voltage (greater than zero volts) at a virtual ground node, a memory array of resistive memory cells in which each resistive memory cell includes a select transistor and a resistive storage element and is coupled to a first column line of a plurality of first column lines, and a first decoder configured to select a set of first column lines for a memory read operation from a selected set of the resistive memory cells. The memory includes read circuitry, and a first column line multiplexer configured to couple each selected first column line of the set of first column lines to the read circuitry during the memory read operation, and configured to couple each unselected first column line of the plurality of first column lines to the virtual ground node during the memory read operation.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: Karthik Ramanan, Jon Scott Choy
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Publication number: 20220101903Abstract: A non-volatile memory includes virtual ground circuitry configured to generate a virtual ground voltage at a virtual ground node, a memory array of memory cells in which each memory cell includes a select transistor and a storage element and is coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a set of first column lines for a memory write operation to a selected set of the memory cells. The non-volatile memory also includes write circuitry configured to receive a write value for storage into the selected set of memory cells, and a first column line multiplexer configured to, during the memory write operation, couple each selected first column line of the set of first column lines to the write circuitry, and couple each unselected first column line of the plurality of first column lines to the virtual ground node.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: Jon Scott Choy, Karthik Ramanan, Padmaraj Sanjeevarao, Jacob T. Williams
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Patent number: 11289144Abstract: A non-volatile memory includes virtual ground circuitry configured to generate a virtual ground voltage at a virtual ground node, a memory array of memory cells in which each memory cell includes a select transistor and a storage element and is coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a set of first column lines for a memory write operation to a selected set of the memory cells. The non-volatile memory also includes write circuitry configured to receive a write value for storage into the selected set of memory cells, and a first column line multiplexer configured to, during the memory write operation, couple each selected first column line of the set of first column lines to the write circuitry, and couple each unselected first column line of the plurality of first column lines to the virtual ground node.Type: GrantFiled: September 25, 2020Date of Patent: March 29, 2022Assignee: NXP USA, Inc.Inventors: Jon Scott Choy, Karthik Ramanan, Padmaraj Sanjeevarao, Jacob T. Williams
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Patent number: 11250898Abstract: As disclosed herein, a memory includes an array of resistive memory cells and a voltage regulator circuit that provides a regulated voltage based on a circuit with a replica resistive storage element. The regulated voltage is applied to a mux transistor of a multiplexer of a column decoder that is used to select a particular column line of a memory array from a set of column lines to provide the proper voltage to the memory cell during a write operation to the memory cell.Type: GrantFiled: April 10, 2020Date of Patent: February 15, 2022Assignee: NXP USA, INC.Inventors: Padmaraj Sanjeevarao, Jacob T. Williams, Karthik Ramanan, Jon Scott Choy
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Publication number: 20210387613Abstract: The present invention relates to a method for having a vehicle (100) follow a desired curvature path (C1), said vehicle (100) comprising at least one differential (10, 20, 30) with a differential lock connected to at least one driven wheel axle (40, 50) of said vehicle (100), said method comprising at least the following steps: —providing (S1) information regarding state of said differential lock, said state being either that said differential lock is activated or unlocked, and when said differential lock is activated: —calculating (S2) a yaw moment, Mdiff, of said vehicle (100), caused by said differential lock; and —compensating (S3) for a deviation from said desired curvature path (C1) caused by said yaw moment, Mdiff, such that a resulting steering angle is equal to or less than a maximum allowed steering angle of said vehicle (100), whereby said compensation is a feed forward compensation. The invention also relates to a control unit, a vehicle, a computer program and a computer readable medium.Type: ApplicationFiled: October 22, 2018Publication date: December 16, 2021Applicant: VOLVO TRUCK CORPORATIONInventors: Leo LAINE, Karthik Ramanan VAIDYANATHAN
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Publication number: 20210319819Abstract: As disclosed herein, a memory includes an array of resistive memory cells and a voltage regulator circuit that provides a regulated voltage based on a circuit with a replica resistive storage element. The regulated voltage is applied to a mux transistor of a multiplexer of a column decoder that is used to select a particular column line of a memory array from a set of column lines to provide the proper voltage to the memory cell during a write operation to the memory cell.Type: ApplicationFiled: April 10, 2020Publication date: October 14, 2021Inventors: Padmaraj Sanjeevarao, Jacob T. Williams, Karthik Ramanan, Jon Scott Choy
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Patent number: 11145382Abstract: A leakage measuring circuit includes a bias input node control circuit and provides a signal indicative of a leakage current through the bias input node. The bias input node control circuit includes a first input to receive an indication of a reference voltage, a second input to receive an indication of a voltage of the bias input node, and an output to bias the bias input node at the reference voltage based on a relationship between the first and second input. A well voltage bias circuit provides a well bias voltage and includes a well bias control circuit including a first input to receive the signal indicative of the leakage current, a second input to receive a signal indicative of a reference leakage current value, and an output for controlling the well bias voltage based on a relationship between the first and second input of the well bias control circuit.Type: GrantFiled: May 11, 2020Date of Patent: October 12, 2021Assignee: NXP USA, Inc.Inventors: Karthik Ramanan, Jon Scott Choy, Jacob T. Williams
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Patent number: 10984846Abstract: A sense amplifier circuit includes a reference path, a cell path, and a comparator circuit. The reference path includes a first current load device and a reference comparison node in which the reference path is coupled to a cell reference circuit during a read, wherein the first current load device includes a control input for controlling a current of the reference path. The cell path includes a second current load device and a cell comparison node in which the cell path is coupled to a memory cell during a read, wherein the second current load device includes a control input for controlling a current of the cell path. The comparator circuit indicates a data value being stored in the memory cell based on a comparison of voltages at the reference and cell comparison nodes. Different signals are provided to the control inputs of the first and second current load devices.Type: GrantFiled: July 10, 2019Date of Patent: April 20, 2021Assignee: NXP USA, Inc.Inventors: Karthik Ramanan, Jon Scott Choy, Jacob Williams
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Publication number: 20210078556Abstract: A control arrangement for a vehicle motion system including a braking function, comprising motion actuators with one or more brake actuators pertaining to the braking function, a first vehicle motion management controller (VMM1) and a second vehicle motion management controller (VMM2), forming a redundant assembly to control the braking function, wherein, in riding conditions, the first vehicle motion management controller controls the brake actuators with a current nominal expected braking performance, while the second vehicle motion management controller (VMM2) is in a waiting-to-operate mode, the control arrangement comprising a hot swap functionality in which the second vehicle motion management controller (VMM2) is configured to take over control of the brake actuators from the first vehicle motion management controller, with the current nominal expected braking performance, in a short time period (SWT) less than one second, preferably less than 0.5 second, preferably less than 0.Type: ApplicationFiled: May 3, 2018Publication date: March 18, 2021Inventors: Leo Laine, Lionel Farres, Christian Oscarsson, Leon Henderson, Johanna Majqvist, Jose Vilca, Kristoffer Tagesson, Karthik Ramanan Vaidyanathan, Nicolas Soulier
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Publication number: 20210012821Abstract: A sense amplifier circuit includes a reference path, a cell path, and a comparator circuit. The reference path includes a first current load device and a reference comparison node in which the reference path is coupled to a cell reference circuit during a read, wherein the first current load device includes a control input for controlling a current of the reference path. The cell path includes a second current load device and a cell comparison node in which the cell path is coupled to a memory cell during a read, wherein the second current load device includes a control input for controlling a current of the cell path. The comparator circuit indicates a data value being stored in the memory cell based on a comparison of voltages at the reference and cell comparison nodes. Different signals are provided to the control inputs of the first and second current load devices.Type: ApplicationFiled: July 10, 2019Publication date: January 14, 2021Inventors: Karthik Ramanan, Jon Scott Choy, Jacob Williams
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Patent number: 10796741Abstract: A word line regulator provides a write word line voltage for an asserted word line and includes a write replica circuit, a reference current path, and a regulator circuit. The write replica circuit is a replica of a write path for writing from a low to high resistance value of a resistive memory element of a memory cell. The word line regulator regulates the word line voltage at a value during the write operation of a low to high resistance value such that a select transistor of the memory cell is used as a source follower to regulate a first node of a resistive element of the memory cell being written. The first node is at a higher write voltage than a second node of the resistive element during the write operation, and the first node is located in a write path between the select transistor and the second node.Type: GrantFiled: October 30, 2019Date of Patent: October 6, 2020Assignee: NXP USA, Inc.Inventors: Jacob T. Williams, Jon Scott Choy, Karthik Ramanan