Abstract: A system for testing circuits of an integrated circuit semiconductor wafer includes a tester system for generating signals for input to the circuits and for processing output signals from the circuits for testing the wafer and a test stack coupled to the tester system. The test stack includes a wafer probe for contacting a first surface of the wafer and for probing individual circuits of the circuits of the wafer, a wafer thermal interposer (TI) layer operable to contact a second surface of the wafer and operable to selectively heat areas of the wafer, and a cold plate disposed under the wafer TI layer and operable to cool the wafer. The system further includes a thermal controller for selectively heating and maintaining temperatures of the areas of the wafer by controlling cooling of the cold plate and by controlling selective heating of the wafer TI layer.

Abstract: Placing a first side of an active thermal interposer device of a thermal management head against a device under test (DUT). Disposing a cold plate against a second side of the active thermal interposer. The DUT includes a die and the active thermal interposer device includes a plurality of zones, each zone of the plurality of zones corresponding to a respective module of the plurality of modules and operable to be selectively heated. Receiving a respective set of inputs corresponding to each zone of the plurality of zones. Performing thermal management of the plurality of modules of the DUT by separately controlling temperature of each zone of the plurality of zones by controlling a supply of coolant to the cold plate, and individually controlling heating of each zone of the plurality of zones.

Abstract: Embodiments of the present invention provide testing systems that perform advanced system level testing of multiple devices in parallel over a network connection that provides access to multiple development stations for improved efficiency and access to system level testing. A rack integrated computer (RIC) is coupled to multiple tester racks of single board computers (SBCs) and provides access to the SBCs as development workstations for use over a computer network (e.g., a customer network). SBCs can provide end level testing of devices like smartphones that include several different devices (DUTs). Access to the SBCs as development workstations can be enforced on an IP level under a development license, and the license may be used from any global location using a static IP address and/or virtual private network, for example.

Abstract: A stand-alone active thermal interposer device for use in testing an unpackaged integrated circuit device under test (DUT), the active thermal interposer device includes a body layer having a first surface and a second surface, wherein the first surface is operable to be disposed adjacent to a cold plate, and a plurality of heating zones defined across a second surface of the body layer, the plurality of heating zones operable to be controlled by a thermal controller to selectively heat and maintain respective temperatures thereof, the plurality of heating zones operable to heat a plurality of areas of the DUT when the second surface of the body layer is disposed adjacent to an interface surface of the DUT during testing of the DUT.

Abstract: An automated test equipment (ATE) includes a test interface board assembly. The test interface board includes a socket configured to provide electrical couplings from the test interface board to a device under test (DUT). The socket is further configured to accept an active thermal interposer (ATI) device while the DUT is disposed in the socket. The socket includes a plurality of spring-loaded roller retention devices configured to retain one or more devices in the socket. The ATE further includes a Z-axis interface plate configured to open the plurality of spring-loaded roller retention devices to enable insertion of the DUT into the socket and an ATI placement plate configured to open the plurality of spring-loaded roller retention devices to enable insertion of the ATI device into the socket.

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

Abstract: Apparatus and method for stack access throttling for synchronous ray tracing. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations to ensure that a size of the active ray tracing stack allocations remains within a threshold; and an execution unit to execute a thread to explicitly request a new ray tracing stack allocation from the ray tracing acceleration hardware, the ray tracing acceleration hardware to permit the new ray tracing stack allocation if the size of the active ray tracing stack allocations will remain within the threshold after permitting the new ray tracing stack allocation.

Abstract: A stand-alone active thermal interposer device for use in testing an unpackaged integrated circuit device under test (DUT), the active thermal interposer device includes a body layer having a first surface and a second surface, wherein the first surface is operable to be disposed adjacent to a cold plate, and a plurality of heating zones defined across a second surface of the body layer, the plurality of heating zones operable to be controlled by a thermal controller to selectively heat and maintain respective temperatures thereof, the plurality of heating zones operable to heat a plurality of areas of the DUT when the second surface of the body layer is disposed adjacent to an interface surface of the DUT during testing of the DUT.

Abstract: Embodiments of the present invention provide testing systems with liquid cooled thermal arrays that can pivot freely in three dimensions allowing surfaces to be brought into even, level, and secure contact, thereby preventing air gaps between surfaces and improving thermal performance. In this way, more DUTs can be tested in parallel within a small test space, overall costs of the test system are reduced, and greater cooling capacity can be provided for testing high-powered devices. Gimbaled mounts can be disposed on a bottom surface of individual thermal interface boards (TIBs) of a test system, and/or on top of individual thermal heads of a thermal array (TA) having a common cold plate (or having multiple cold plates).

Abstract: Placing a first side of an active thermal interposer device of a thermal management head against a device under test (DUT). Disposing a cold plate against a second side of the active thermal interposer. The DUT includes a die and the active thermal interposer device includes a plurality of zones, each zone of the plurality of zones corresponding to a respective module of the plurality of modules and operable to be selectively heated. Receiving a respective set of inputs corresponding to each zone of the plurality of zones. Performing thermal management of the plurality of modules of the DUT by separately controlling temperature of each zone of the plurality of zones by controlling a supply of coolant to the cold plate, and individually controlling heating of each zone of the plurality of zones.

Abstract: A test apparatus comprising a tester interface board (TIB) affixed in a slot of a tester rack, wherein the TIB comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT). The test apparatus further comprises a carrier comprising an array of DUTs, wherein the carrier is operable to slide into the slot of the tester rack, and wherein each DUT in the array of DUTs aligns with a respective socket on the TIB. Further, the test apparatus comprises a plurality of socket covers, wherein each socket cover of the plurality of socket covers is operable to actuate a top portion of each DUT of the array of DUTs in the carrier.

Abstract: A testing apparatus includes a tester rack with a plurality of slots where at least one slot in the tester rack is a dedicated slot operable to receive a test interface board (TIB) from a back of the tester rack, where the back of the tester rack is opposite a front of a tester rack, and where the front of the tester rack faces a handler and a front-facing elevator. The apparatus also includes a handler operable to load devices under test (DUTs) onto the TIB and a front-facing elevator move the TIB from the dedicated slot to an available slot in the tester rack, wherein the available slot includes power electronics operable to connect to the TIB to test devices under test (DUT) disposed on the TIB.

Abstract: In some examples, a computing device may determine that an issue (e.g., crash, restart etc.) occurred, gather context data (e.g., logs, device profile, etc.) associated with the issue, and generate a contact address to technical support based on the context data. The computing device may upload the context data to a location accessible to a server. After a user of the computing device initiates a communication to technical support using the contact address, the server may automatically route the call, based on the contact address, to a particular technician that has experience addressing the issue. The server may retrieve the context data and use machine learning to determine recommendations to address the issue. The machine learning may prioritize the recommendations and provide the context data and the prioritized recommendations to enable the particular technician to quickly resolve the issue.

Abstract: Provided is a temperature control apparatus, comprising: a mounting unit including a mounting surface for mounting a board-shaped test object on which a plurality of devices are formed; a plurality of heaters provided for each of a plurality of zones into which the mounting surface is divided, which heats corresponding one of the plurality of zones; a device temperature acquiring unit which acquires device temperature data according to a temperature measurement value in a device under test connected to a probe for an operation test among the plurality of devices of the test object; and a temperature control unit which controls two or more of the heaters corresponding to two or more of the zones on each of which at least part of the device under test is mounted, thereby closing a gap between a temperature indicated by the device temperature data and a first target temperature.

Abstract: A system for testing circuits of an integrated circuit semiconductor wafer includes a tester system testing the circuits of the wafer and a test stack coupled to the tester system. The test stack includes a wafer probe for contacting a first surface of the wafer and for probing individual circuits of the circuits of the wafer, a wafer scale active thermal interposer layer operable to contact a second surface of the wafer and containing a plurality of thermal zones corresponding to a die layout of the wafer and further operable to selectively heat areas of the wafer. The thermal zones are thermally isolated using a plurality of thermal resistance structures disposed between the thermal zones.

Abstract: An active thermal interposer (ATI) device for use in testing integrated circuit device under test (DUT) having thermal isolation structures. The ATI device includes a formation having a first surface and a second surface, wherein the first surface is operable to be disposed adjacent to a cold plate, and a plurality of heating zones defined across a second surface of the formation, the plurality of heating zones operable to be controlled by a thermal controller to selectively heat and maintain respective temperatures thereof, the plurality of heating zones operable to heat a plurality of areas of the DUT when the second surface of the formation is disposed adjacent to an interface surface of the DUT during testing of the DUT. The ATI device includes a plurality of thermal resistance structures configured to resist thermal conductance between the plurality of heating zones.

Abstract: Methods and systems are disclosed that include receiving problem information from a user interface at a resolution identification system, receiving product information at the resolution identification system, and performing machine learning analysis of the problem information and the product information. The machine learning analysis produces one or more model outputs, and is performed by a machine learning system of the resolution identification system, using one or more machine learning models. Each of the one or more machine learning models produces a corresponding one of the one or more model outputs. Such a method can further include generating resolution information by performing an action identification operation using the one or more model outputs, and outputting the resolution information from the resolution identification system. The resolution information is output to the user interface.

Abstract: A testing apparatus comprises a test interface board comprising a plurality of socket interface boards, wherein each socket interface board comprises: a) an open socket to hold a DUT; b) a discrete active thermal interposer comprising thermal properties and operable to make thermal contact with the DUT; c) a superstructure operable to contain the discrete active thermal interposer; and d) an actuation mechanism operable to provide a contact force to bring the discrete active thermal interposer in contact with the DUT.

Abstract: An apparatus for thermal control of a device under test (DUT) includes a cooling structure operable to provide cooling, the cooling structure operable to inlet cooling material via an inlet port thereof and operable to outlet cooling material via an outlet port thereof, a variable thermal conductance material (VTCM) layer disposed on a surface of the cooling structure, and a heater layer operable to generate heat based on an electronic control, and wherein the VTCM layer is operable to transfer cooling from the cooling structure to the heater layer. A thermal interface material layer is disposed on the heater layer. The thermal interface material layer is operable to provide thermal coupling and mechanical compliance with respect to the DUT. The apparatus includes a compression mechanism for providing compression to the VTCM layer to vary a thermal conductance of the VTCM layer. The compression mechanism is also for decoupling the VTCM layer from the heater layer.

Abstract: Embodiments of the present invention provide testing systems with liquid cooled thermal arrays that can pivot freely in three dimensions allowing surfaces to be brought into even, level, and secure contact, thereby preventing air gaps between surfaces and improving thermal performance. In this way, more DUTs can be tested in parallel within a small test space, overall costs of the test system are reduced, and greater cooling capacity can be provided for testing high-powered devices. Gimbaled mounts can be disposed on a bottom surface of individual thermal interface boards (TIBs) of a test system, and/or on top of individual thermal heads of a thermal array (TA) having a common cold plate (or having multiple cold plates).