Patents by Inventor Karthik Rao
Karthik Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240085964Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Sriram Sambamurthy, Sriram Sundaram, Indrani Paul, Larry David Hewitt, Anil Harwani, Aaron Joseph Grenat, Dana Glenn Lewis, Leonardo Piga, Wonje Choi, Karthik Rao
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Publication number: 20240069186Abstract: A radar transceiver includes a phase shifter that is controlled to apply an induced phase shift in a first subset of chirp signals of a frame of chirp signals, which also includes a second subset of chirp signals in which no phase shift is applied. Other circuitry generates digital signals based on received reflected signals, which are based on transmitted signals. Processing circuitry performs a Fast Fourier Transform (FFT) on a first subset of digital signals, corresponding to the first subset of chirp signals, to generate a first range-Doppler array, and performs a FFT on the second subset of digital signals, corresponding to the second subset of chirp signals, to generate a second range-Doppler array; identifies peaks in the first and second range-Doppler arrays to detect an object; and compares a phases of peaks at corresponding positions in the first and second range-Doppler arrays to determine a measured phase shift between the two peaks.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Inventors: Sandeep Rao, Karthik Subburaj
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Patent number: 11886224Abstract: A processing unit of a processing system compiles a priority queue listing of a plurality of processor cores to run a workload based on a cost of running the workload on each of the processor cores. The cost is based on at least one of a system usage policy, characteristics of the workload, and one or more physical constraints of each processor core. The processing unit selects a processor core based on the cost to run the workload and communicates an identifier of the selected processor core to an operating system of the processing system.Type: GrantFiled: July 31, 2020Date of Patent: January 30, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Leonardo De Paula Rosa Piga, Karthik Rao, Indrani Paul, Mahesh Subramony, Kenneth Mitchell, Dana Glenn Lewis, Sriram Sambamurthy, Wonje Choi
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Publication number: 20240004453Abstract: Methods and systems are disclosed for managing the power consumed by cores of a system on chip (SoC). Techniques disclosed include obtaining application information that is indicative of an application being executed on the cores, detecting a workload associated with the application, and limiting one or more operating frequencies of the cores responsive to the detection of the workload. Techniques disclosed also include profiling the detected workload and limiting the one or more operating frequencies of the cores based on the profiling.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Ashwini Chandrashekhara Holla, Alexander S. Duenas, Xinzhe Li, Indrani Paul, Karthik Rao
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Publication number: 20240004444Abstract: Methods and systems are disclosed for managing performance states of a data fabric of a system on chip (SoC). Techniques disclosed include determining a performance state of the data fabric based on data fabric bandwidth utilizations of respective components of the SoC. A metric, characteristic of a workload centric to cores of the SoC, is derived from hardware counters, and, based on the metric, it is determined whether to alter the performance state.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Karthik Rao, Indrani Paul, Dana Glenn Lewis, Brett Danier Anil Ramautarsingh, Jeffrey Ka-Chun Lui, Prasanthy Loganaathan, Jun Huang, Ho Hin Lau, Zhidong Xu
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Patent number: 11829222Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.Type: GrantFiled: December 18, 2020Date of Patent: November 28, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Sriram Sambamurthy, Sriram Sundaram, Indrani Paul, Larry David Hewitt, Anil Harwani, Aaron Joseph Grenat, Dana Glenn Lewis, Leonardo Piga, Wonje Choi, Karthik Rao
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Patent number: 11726837Abstract: In some examples, thermal aware optimization logic determines a characteristic (e.g., a workload or type) of a wavefront (e.g., multiple threads). For example, the characteristic indicates whether the wavefront is compute intensive, memory intensive, mixed, and/or another type of wavefront. The thermal aware optimization logic determines temperature information for one or more compute units (CUs) in one or more processing cores. The temperature information includes predictive thermal information indicating expected temperatures corresponding to the one or more CUs and historical thermal information indicating current or past thermal temperatures of at least a portion of a graphics processing unit (GPU). The logic selects the one or more compute units to process the plurality of threads based on the determined characteristic and the temperature information. The logic provides instructions to the selected subset of the plurality of CUs to execute the wavefront.Type: GrantFiled: November 4, 2021Date of Patent: August 15, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Karthik Rao, Shomit N. Das, Xudong An, Wei Huang
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Publication number: 20230108234Abstract: A processing system adjusts an operating state of one or more processors during execution of a workload based on a command paired with the workload. The command specifies a desired operating state or a performance or power efficiency target operational goal and is enqueued asynchronously with the workload. A power management controller reads the command synchronously with dispatching the workload to the processor. By asynchronously enqueuing the tag with the workload, the processing system tunes the operating state of the processor to reach higher performance, higher performance per watt, and/or higher energy efficiency during processing of the workload.Type: ApplicationFiled: September 28, 2021Publication date: April 6, 2023Inventors: Joseph L. Greathouse, Stephen Kushnir, Karthik Rao, Leopold Grinberg
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Publication number: 20230088994Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.Type: ApplicationFiled: November 23, 2022Publication date: March 23, 2023Inventors: Karthik RAO, Indrani Paul, Donny YI, Oleksandr KHODORKOVSKY, Leonardo DE PAULA ROSA PIGA, Wonje CHOI, Dana G. LEWIS, Sriram SAMBAMURTHY
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Patent number: 11568167Abstract: In some embodiments, a first plurality of representations are extracted from a first data set. A first set of distributions are generated based on the first plurality of representations. A machine learning model is trained based on the first plurality of representations and the first set of distributions. A second plurality of representations are extracted from a second data set different from the first data set. The machine learning model is executed based on the second plurality of representations to produce a second set of distributions. An anomaly score is determined for each datum from the second data set to produce a set of anomaly scores. The set of anomaly scores are determined based on the first set of distributions and the second set of distributions. A notification is generated when at least one anomaly score from the set of anomaly scores is larger than a predetermined threshold.Type: GrantFiled: May 25, 2022Date of Patent: January 31, 2023Assignee: Arthur AI, Inc.Inventors: Keegan E. Hines, John P. Dickerson, Karthik Rao, Rowan Cheung, Reese M. E. Hyde
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Patent number: 11556250Abstract: A system including a stack of two or more layers of volatile memory, such as layers of a 3D stacked DRAM memory, places data in the stack based on a temperature or a refresh rate. When a threshold is exceeded, data are moved from a first region to a second region in the stack, the second region having one or both of a second temperature lower than a first temperature of the first region or a second refresh rate lower than a first refresh rate of the first region.Type: GrantFiled: July 27, 2020Date of Patent: January 17, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Jagadish B. Kotra, Karthik Rao, Joseph L. Greathouse
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Patent number: 11543877Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.Type: GrantFiled: March 31, 2021Date of Patent: January 3, 2023Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULCInventors: Karthik Rao, Indrani Paul, Donny Yi, Oleksandr Khodorkovsky, Leonardo De Paula Rosa Piga, Wonje Choi, Dana G. Lewis, Sriram Sambamurthy
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Publication number: 20220383038Abstract: In some embodiments, a first plurality of representations are extracted from a first data set. A first set of distributions are generated based on the first plurality of representations. A machine learning model is trained based on the first plurality of representations and the first set of distributions. A second plurality of representations are extracted from a second data set different from the first data set. The machine learning model is executed based on the second plurality of representations to produce a second set of distributions. An anomaly score is determined for each datum from the second data set to produce a set of anomaly scores. The set of anomaly scores are determined based on the first set of distributions and the second set of distributions. A notification is generated when at least one anomaly score from the set of anomaly scores is larger than a predetermined threshold.Type: ApplicationFiled: May 25, 2022Publication date: December 1, 2022Inventors: Keegan E. HINES, John P. DICKERSON, Karthik RAO, Rowan CHEUNG, Reese M. E. HYDE
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Publication number: 20220317757Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Inventors: Karthik RAO, Indrani PAUL, Donny YI, Oleksandr KHODORKOVSKY, Leonardo DE PAULA ROSA PIGA, Wonje CHOI, Dana G. LEWIS, Sriram SAMBAMURTHY
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Patent number: 11436060Abstract: Systems, apparatuses, and methods for proactively managing inter-processor network links are disclosed. A computing system includes at least a control unit and a plurality of processing units. Each processing unit of the plurality of processing units includes a compute module and a configurable link interface. The control unit dynamically adjusts a clock frequency and a link width of the configurable link interface of each processing unit based on a data transfer size and layer computation time of a plurality of layers of a neural network so as to reduce execution time of each layer. By adjusting the clock frequency and the link width of the link interface on a per-layer basis, the overlapping of communication and computation phases is closely matched, allowing layers to complete more quickly.Type: GrantFiled: August 27, 2019Date of Patent: September 6, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Karthik Rao, Abhinav Vishnu
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Publication number: 20220206916Abstract: Methods and apparatus manage data in memories disposed in a stacked relation with respect to one or more processors. The method includes receiving at least one hint indicating future processor usage of a software component, where the future processor usage is indicative of future usage of the one or more processors when executing the software component or a code section of the software component. In some implementations, the method includes selecting a memory location in the memories for data used by the software component based on the hint.Type: ApplicationFiled: December 28, 2020Publication date: June 30, 2022Inventors: KARTHIK RAO, LEONARDO DE PAULA ROSA PIGA
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Publication number: 20220107849Abstract: In some examples, thermal aware optimization logic determines a characteristic (e.g., a workload or type) of a wavefront (e.g., multiple threads). For example, the characteristic indicates whether the wavefront is compute intensive, memory intensive, mixed, and/or another type of wavefront. The thermal aware optimization logic determines temperature information for one or more compute units (CUs) in one or more processing cores. The temperature information includes predictive thermal information indicating expected temperatures corresponding to the one or more CUs and historical thermal information indicating current or past thermal temperatures of at least a portion of a graphics processing unit (GPU). The logic selects the one or more compute units to process the plurality of threads based on the determined characteristic and the temperature information. The logic provides instructions to the selected subset of the plurality of CUs to execute the wavefront.Type: ApplicationFiled: November 4, 2021Publication date: April 7, 2022Inventors: KARTHIK RAO, SHOMIT N. DAS, XUDONG AN, WEI HUANG
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Publication number: 20220100249Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.Type: ApplicationFiled: December 18, 2020Publication date: March 31, 2022Inventors: Sriram Sambamurthy, Sriram Sundaram, Indrani Paul, Larry David Hewitt, Anil Harwani, Aaron Joseph Grenat, Dana Glenn Lewis, Leonardo Piga, Wonje Choi, Karthik Rao
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Publication number: 20210406092Abstract: A processing unit of a processing system compiles a priority queue listing of a plurality of processor cores to run a workload based on a cost of running the workload on each of the processor cores. The cost is based on at least one of a system usage policy, characteristics of the workload, and one or more physical constraints of each processor core. The processing unit selects a processor core based on the cost to run the workload and communicates an identifier of the selected processor core to an operating system of the processing system.Type: ApplicationFiled: July 31, 2020Publication date: December 30, 2021Inventors: Leonardo DE PAULA ROSA PIGA, Karthik RAO, Indrani PAUL, Mahesh SUBRAMONY, Kenneth MITCHELL, Dana Glenn LEWIS, Sriram SAMBAMURTHY, Wonje CHOI
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Patent number: 11194634Abstract: In some examples, thermal aware optimization logic determines a characteristic (e.g., a workload or type) of a wavefront (e.g., multiple threads). For example, the characteristic indicates whether the wavefront is compute intensive, memory intensive, mixed, and/or another type of wavefront. The thermal aware optimization logic determines temperature information for one or more compute units (CUs) in one or more processing cores. The temperature information includes predictive thermal information indicating expected temperatures corresponding to the one or more CUs and historical thermal information indicating current or past thermal temperatures of at least a portion of a graphics processing unit (GPU). The logic selects the one or more compute units to process the plurality of threads based on the determined characteristic and the temperature information. The logic provides instructions to the selected subset of the plurality of CUs to execute the wavefront.Type: GrantFiled: December 14, 2018Date of Patent: December 7, 2021Assignee: Advanced Micro Devices, Inc.Inventors: Karthik Rao, Shomit N. Das, Xudong An, Wei Huang