Patents by Inventor Karthik Reddy Neravetla

Karthik Reddy Neravetla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Independent asynchronous framework for embedded subsystems
    Patent number: 10146296
    Abstract: An integrated circuit is provided with an independent power framework for a first subsystem and another independent power framework for a processor subsystem that receives messages from the first subsystem.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 4, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Kenneth Gainey, Eunjoo Hwang, Karthik Reddy Neravetla, Jen-Jung Hsu
  • INDEPENDENT ASYNCHRONOUS FRAMEWORK FOR EMBEDDED SUBSYSTEMS
    Publication number: 20160132097
    Abstract: An integrated circuit is provided with an independent power framework for a first subsystem and another independent power framework for a processor subsystem that receives messages from the first subsystem.
    Type: Application
    Filed: November 6, 2014
    Publication date: May 12, 2016
    Inventors: Kenneth Gainey, Eunjoo Hwang, Karthik Reddy Neravetla, Jen-Jung Hsu
  • Phase locked loop clock divider utilizing a high speed programmable linear feedback shift register with a two stage pipeline feedback path
    Patent number: 6556647
    Abstract: An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register with a two stage pipeline in its feedback path. A plurality of “pre-load” flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop circuits and multiplexers. The PLFF circuits hold pre-calculated initial LFSR sequence values to be loaded into the LFSR flip flop circuits. The load enable signal to the PLFF multiplexers and to the LFSR multiplexers is low for three successive input clock cycles. The present invention is capable of operating at high frequencies due to a shortened timing critical feedback path.
    Type: Grant
    Filed: May 1, 2002
    Date of Patent: April 29, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Karthik Reddy Neravetla